Electronic Design

Debug Platform Targets SoCs Based On Embedded CPUs

Deep insight into the behavior of complex system-on-a-chip (SoC) designs and on-chip communications is more critical than ever due to the onslaught of designs based on embedded processors. Novas Software's nESL debug platform endeavors to help the cause by extending the company's existing Verdi automated debug system to bridge the RTL and system/software domains.

System-level methodologies are gaining ground in both embedded-processor designs and verification environments. So, Novas built the nESL platform to address the system level.

First, the platform offers full SystemC tracing that understands the SystemC class libraries. Users benefit from having the complexities of C/C++ hidden from them and can concentrate on SystemC itself.

Second, and probably more importantly, nESL offers a comprehensive transaction-analysis environment. Transaction data can come from numerous sources, including SystemC SCV and Verisity e sequence descriptions. Designers can view a variety of transaction styles, including split and overlapping transactions.

The nESL platform presents transactions in a spreadsheet format for analysis. This lets designers filter and sort transactions to analyze bus loading or perform source and destination checks.

Another key technology is what Novas calls its Open Transaction Interface (OTI), which streamlines the capture and storage of transaction data. With it, designers can easily convert signal information from HDL coding, as well as proprietary bus formats, into transactions for abstract viewing. Also with the OTI, third parties can provide converters and other tools to output transactions.

Sold as an option to the Verdi automated debug system, list prices for nESL start at $6000 for a one-year license.

Novas Software

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