Pressure is mounting on verification engineers to reduce the time and cost of ensuring that system designs are thoroughly debugged. The economy heading into 2009 demands that designers begin the verification process as early and at as high an abstraction level as possible, even in the behavioral stages. Doing so helps eliminate functional errors.
Gaining efficiency in the verification process has a number of salutatory effects. For one, it means delivering more advanced functionality in less time and with greater quality. For another, it facilitates downstream improvements in the development cycle as more engineering teams learn to reuse their behavioral testbenches at lower levels of abstraction. Finally, it costs less to correct problems earlier in the cycle.
Further, the trend toward intellectual-property (IP) reuse is accelerating, driven by broader acceptance of SystemVerilog (www.systemverilog.org) and its native constructs that facilitate IP reuse. With system-on-a-chip (SoC) design moving to smaller geometries as market windows shrink and the challenges of effective resource utilization remain the same, design will involve increasing integration and decreasing design creation as we now know it. Proven IP blocks and subsystems that can be quickly and easily integrated, and therefore require minimal support, will become the norm.
While many EDA tool vendors offer extensive catalogs of both vertical and horizontal IP, there’s a growing focus on quality and portability. Socketable IP is gaining in use as it provides an intuitive integration method and enables designers to be much more self-sufficient. It can be developed, released, and maintained efficiently to reduce investment from the factory or field. It also conforms to consistent industry standards, is portable between a given vendor’s devices, and enables much more effective reuse.
TAKING ADVANTAGE OF IP • Easily integrated IP will be delivered in larger blocks and ultimately evolve into integrated subsystems (both hardware and software) and even platforms. Pre-verification of components will be common, and EDA flows will adapt to efficiently model, analyze, integrate, and verify more complex IP.
The combination of this design trend and the tightening of the capital market will result in a two-tier IP provider business: one set of small, niche companies meeting very specific needs and one set of larger companies that will acquire many of the smaller and mid-sized players as they grow. Meanwhile, companies that have created IP for internal use will begin getting into the business of becoming IP providers to the broader market. To facilitate that, they’ll enlist the services of third parties that can ensure integration and handle the marketing, legal, and support issues required by IP consumers.
How designers deal with software integration is also changing, with the influence of software development becoming more pronounced. So-called “software-driven” verification methodologies, centering on virtual platforms, are finding increased usage in software validation and testbench development (see the figure). And as portions of the virtual platform itself are verified as equivalent to their corresponding registertransfer level (RTL), it becomes a golden or reference executable specification for the rest of the design process.
With design teams adopting techniques to start embedded software development as early as possible and to make it as productive as possible, links between virtual platforms and hardware-assisted simulation like emulation and FPGA prototypes gain importance. Otherwise, how will designers find software bugs manifested in hardware, or vice versa?
The need for emulation grows more acute due to the increasing complexity of debugging the embedded portion of systems. To be effective, the emulation system must have a software-aware debugging environment to track a bug in hardware coming from the software debugger.
Traditional emulation systems don’t suffice because they execute at sub-megahertz speeds and don’t have the software-aware debugging environment. Prototyping systems are fast but lack the software-aware debugging environment as well.
A major benefit of emulation is that it provides an all-in-one system for hardware debugging and embedded software validation. Hardware designers and software developers can share the same system and design representations and debug hardware/software interactions.
Yet another trend in 2009 will be a greater emphasis on the testbench itself. Unlike the synthesizable (device under test) logic, the testbench is mostly behavioral, and it isn’t a good candidate for synthesis. However, with the advent of SystemVerilog, both transactors and agitators need to be studied and understood in terms of compute time and acceleration.
Acceleration with testbenches present will not achieve emulation-like speeds, but an acceleration factor of five to 10 times is doable. Cooperation among EDA vendors is imperative to yield worthwhile solutions that benefit the vendors and the user community.
Testbench generation is evolving as well, with hardware design language (HDL) simulators and directed tests yielding to automated random test generation based on a design specification. Some EDA vendors provide so-called “intelligent verification” tools. These let the design automatically direct test generation, accounting for complex design structure and buried coverage areas.
ESL synthesis is moving from early adopters to broader proliferation. High-level synthesis will have tighter links to physical implementation flows with increasing emphasis on poweraware ESL synthesis in addition to area and timing optimization.