Electronic Design

Design Compiler Continues To See Refinement

Some 20 years after its initial, landscape-changing release of Design Compiler, Synopsys continues to refine and improve its flagship synthesis product. Design Compiler 2007 extends topographical technology to accelerate design closure for designs utilizing advanced low power and test techniques, boosting designers’ productivity and IC performance. Topographical technology allows designers to accurately estimate a chip’s power consumption during synthesis and address any power issues early in the design cycle. Moreover, topographical technology supports new test compression technology in Design Compiler 2007 to achieve high test quality while reducing test time and test data volume by more than 100 times.

According to at least one beta user, the application of topographical technology in Design Compiler 2007 resulted in performance predictions made by synthesis that correlated within 5% of physical implementation results. Further, Design Compiler 2007 reduced chip area by an average of 5% while meeting aggressive performance targets.

Topographical technology is said to deliver tight correlation between performance results seen during synthesis and what is achieved after layout. This eliminates the need for time-consuming iterations between RTL synthesis and physical layout to achieve design closure. Design Compiler shares technologies and infrastructure with the Galaxy Design Platform physical design solution to deliver a consistent and highly predictable RTL-to-GDSII path.

Design Compiler 2007 includes several upgraded synthesis technologies such as adaptive retiming and power-driven clock gating, to deliver an average 8% higher performance, 4% smaller area, and 5% ower power consumption compared to the previous release. In addition, the Synopsys Formality equivalence checking solution has been enhanced to independently and thoroughly verify these technologies, thereby allowing designers to achieve higher performance without sacrificing verification.

The Design Compiler RTL synthesis suite encompasses advanced optimizations, complete low-power management, full design-for-test (DFT)/automatic test pattern generation (ATPG), seamless formal verification, and an extensive library of intellectual property (IP) components. Design Compiler 2007 is available immediately; contact Synopsys directly for pricing information.

Synopsys
www.synopsys.com

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