Electronic Design

Design Flows Must Evolve Toward DFM Awareness

Our current concept of DFM is not really manufacturing-aware. With designs scaling down to 130 nm and below and process complexity increasing correspondingly, the impact of process-induced variation on interconnect becomes more dramatic. To ensure the circuit's robustness against these manufacturing-induced (or process-induced) variations, two things must happen.

First, the designer must consider worst-case device models, as well as worst-case interconnect models, for both verification and characterization of circuit performance. Yet designers don't seriously consider worst-case interconnect models in their analysis. Why? Because interconnect performance metrics like the delay variation depend not only on the process technology, but also on the physical design details of the specific interconnect being analyzed by network designers. Therefore, this issue is either ignored or insufficiently addressed.

Second, the designer has to resolve this issue from a design-flow point of view and not from a point-tool point of view. Today, most DFM activities focus on resolution enhancement technology (RET).

What is the final goal for DFM? DFM must consider both deterministic and non-deterministic yield. Thus, the existing nanometer design flows need to evolve into actual (or practical) DFMaware design flows. For example, timing analysis, verification, and closure are no longer enough for signoff. When designers verify timing, they need to use DFM data. DFM is a process model that comes from the foundries or IDMs in one of two forms: rules or models. For nanometer design, DFM rules have limitations, and models can improve yield.

Thus, design flows need to add accurate worst-case interconnect models to assess and maximize design-related yield, especially parametric yield. Based on that, our goal, as a DFM software supplier, is to make timing analysis evolve into DFMaware analysis with accurate worst-case interconnect models.

DFM companies provide and use models for their tools and flows. What's really needed is accurate model-based and

DFM-aware design. Due to the sub-wavelength problem, designers must have their simulation data match the real silicon results to predict performance and improve yield. This holds true particularly for design below 130 nm. Model-based, DFM-aware design can improve timing analysis, as well as power, noise, and delay analysis, leading to increases in final yields.

Again, it's impossible to meet the design target without considering interconnect, since these designs now require standardized and accurate DFM-aware models that can be easily incorporated into existing design flows.

For DFM-aware design, designers used to apply the "awareness" to the overall design flow, which considers only RET, chemical-mechanical polishing, optical proximity correction, and lithography simulation. Now, the designer must consider circuit performance parameters, such as power, noise, signal integrity, and timing analysis. RET is definitely meaningful, but without considering circuit performance, DFM is meaningless.

Interconnect can't be ignored below 130 nm. Transistor models fall short. RC delay increases dramatically as processes scale down. The RC delay of interconnect lines is 2.12 times larger than gate delay at 130 nm; 2.75 times larger at 90 nm; 4.29 times larger at 65 nm; and 7.56 times larger at 45 nm. Up until the emergence of DFM-aware design, this has been ignored or insufficiently addressed.

New DFM-aware methodologies add process-variation data using statistical approaches along with timing analysis for more accurate and practical DFM-aware models. The statistically based approach to the characterization of realistic, worst-case interconnect models accounts for process-induced variations.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.