For some time now, the EDA industry has stagnated from various perspectives. It’s definitely stagnated when it comes to revenue. One gets tired of hearing the phrase “$4-billion-industry” applied to EDA, but that’s been the case for several years now, even as semiconductor revenues continue to escalate. Certainly something is wrong with this picture—EDA tools and technologies are invaluable to the continuing validity of Moore’s Law and to the relentless rise in functionality borne on silicon as a function of area.
EDA has also stagnated in terms of technological growth. Many feel that the RTL-to-GDSII flow has become more or less commoditized, and that future growth—from both the technological and economic perspectives—would come from the extreme front and back ends of the design flow. At the front end, most pin their hopes on electronic system-level (ESL) flows. Some large system houses (Nokia, Samsung, STMicroelectronics, and Texas Instruments come to mind) gained considerable advantages by installing ESL methodologies into their design flows. But ESL has yet to make its way into the mainstream. While it may become a significant revenue producer for EDA vendors, the wait continues.
That takes us to the back end of the design flow, which is steadily emerging as the Great Hope for EDA. Why the back end and not the front end? My best guess is that as semiconductor makers seek to leverage more advanced fabrication technologies, they’re placing larger and larger bets on the success of each generation of silicon. The deep back end of the design process is their last and best hope to salvage yield, which gets harder to come by with successive generations of process technology.
So semiconductor makers are now turning to the EDA community for help. What’s been the EDA community’s response? A couple of relatively new “design-for” buzzwords: “design for manufacturing,” or DFM (sardonically referred to by some wags as “dollars for me”) and “design for yield,” or DFY (same wags: “dollars for you”), which are variations on a common theme. Both hinge on the notion that the fundamental sources of declining yields have changed. At larger design geometries, the limits of yield are defined by random defects stemming from particle contamination. But at the deep-submicron geometries, it’s lithography-related anomalies that dominate yield limits.
As recently as last September, I looked into the current state of DFM and found a promising, if not completely fulfilling, picture (see “The Truth About Design For Manufacturing,” Sept. 29, 2005, ED Online 11130). The elephant in the room when it came to DFM was the lack of process information available to designers. Without detailed, specific knowledge of a specific fab line and its potential image-distorting tendencies, there’s very little that designers can do to positively influence yield beyond blind adherence to design rules. And, in turn, there’s little in the way of true design for manufacturing.
This is obviously much less of an issue for integrated device manufacturers (IDMs) who own their manufacturing facilities. But for the much larger fabless semiconductor community, it’s a huge stumbling block. They have access only to merchant fabs, and the EDA tools at their disposal were, in general, lacking in their application of fab-specific data that would help them design around yield-limiting lithographic bugaboos. Whereas IDMs have much less resistance to the upstream propagation of process data, the merchant fabs tend to hold such sensitive information a little closer to the vest.
Quite a bit has changed since September, though. For example, Cadence Design Systems recently rolled out its Virtuoso RET Suite, which attempts to address the problem through precise modeling of the distortions inherent in submicron lithography (see “Lithographic Awareness Reaches Front-End Design Tools, ED Online 12197). Cadence tried to get around the sensitivity of process information by encapsulating it in “Process Model Files,” a new proposal for a standard, secure courier of detailed and confidential manufacturing information that’s seamlessly integrated to the Cadence Virtuoso environment.
Now, Mentor Graphics has redoubled its DFM efforts with the introduction of Calibre LFD (Litho-Friendly Design), which purports to address the management of process variability in the early stages of physical design creation. The foundation of Calibre LFD is the “LFD kit,” which is a set of data provided to layout designers by foundries and fabs. It’s analogous to the design-rule-checking kit central to earlier generations of DFM tools.
LFD kits include energy, dose, and mask bias considerations; RET recipes; process models; and the parametrizable rules to be checked. All of this information is presented in a common results database. Designers can use the LFD kits to run simulations to see how a layout will print under a particular lithographic process window. The goal is to drive the design toward an “LFD-clean” as well as a “DRC-clean” signoff. Calibre LFD is intended to take physical verification out of a purely rule-based paradigm to one that incorporates both rules and models.
The concept of “litho-friendly design,” as exemplified in Calibre LFD, speaks directly to the issues that plagued earlier DFM tools—specifically, the lack of usable process data within the physical design flow. Because it relies on real process data, Calibre LFD is aware of the process window at all stages of the flow. It calculates a Design Variability Index (DVI), which provides a way to measure how resilient a given design is to process variation. A lower DVI value indicates a more robust design. The DVI compares different layout implementations and helps designers select the one that’s least sensitive to variations (Fig. 1).
Calibre LFD’s simulation results also include recommendations about how to modify the design to improve yield, which can then be made in the designer’s preferred layout environment. In the past, only the manufacturer had the wherewithal to make such changes. Litho-friendly design is an effort to put the designer back into the driver’s seat.
Part of the reason why process data was so foreign to designers is because it’s abstract, and can be difficult to relate to the nuts and bolts of a layout. Calibre LFD plugs into the designer’s existing flow as an iterative step (Fig. 2). The process data is expressed in the LFD kits; therefore, only the kits need to be aware of the details regarding pattern transfer at the foundry, including OPC recipes. With the process details now abstracted away from the designer, they can focus solely on layout.
Tools like Cadence’s Virtuoso RET Suite and Mentor’s Calibre LFD both show promise of driving toward a true form of DFM. Both seek to bridge the gap between design and manufacturing in a way that will empower designers while protecting the fabs’ sensitive process recipes.