In EDA, two primary areas still have room for innovation. One is at high levels of abstraction (above RTL), where a stalwart band of startups as well as one or two of EDA's heavier commercial hitters continue to seek a solid and predictable path from an idealized functional specification to a concrete physical representation of a complex system-on-a-chip (SoC) design.
The other fertile ground for innovation sits at the extreme back end of the design cycle, where functionally verified netlists cross the chasm into GDSII. At this point, squirrely physics come into play when the features being printed on silicon are smaller than the wavelength of the light used to pattern them. As silicon feature sizes have slid down the scale from the submicron range to the nanometer realm, the well-defined geometries crafted by designers into a layout become more difficult to preserve in photolithography (see the figure).
There's little argument that post-layout processing techniques such as reticle enhancement technology (RET), optical-proximity correction (OPC), and the like begin to run out of steam at nanometer scales. Rather than try to correct the problems after actual design work is completed, it's self-evident that process knowledge must be built into the design flow itself. The question is determining how to accomplish that goal. How are designers to overcome the yield and process-variability issues that can overwhelm their designs at 90 nm and down?
The three following expert viewpoints (plus a fourth to be found at www.electronicdesign.com, Drill Deeper 16304) represent some of the industry's thinking on where the EDA industry must go to make true design for manufacturing (DFM) an achievable part of designers' flows:
• Dwayne Burek, senior product director in the Design Implementation Business Unit at Magma Design Automation, looks at the development of a design flow with all the elements of true DFM.
• Phil Bishop, president and CEO of Pyxis Technology, discusses the requirement for manufacturing-aware routing to overcome variability issues.
• Won-Young Jung, CTO and founder of Nanno Solutions, delves into how design flows must evolve toward DFM awareness, especially when it comes to interconnects.
• Nitin Deo, vice president of marketing and business development at Clear Shape Technologies, discusses what it will take to return to a "what-you-see-is-what-you-get" world when it comes to layout versus silicon patterning (see "Bringing Silicon Contours Into The Designer's World," Drill Deeper 16304).
DWAYNE BUREK is the senior product director of the Design Implementation Business Unit at Magma Design Automation, San Jose, Calif. Since joining Magma Design Automation in 2003, he has held R&D and product marketing roles in DFT and DFM. Before that, he spent seven years in the CAD group at BNR (now Nortel Networks) and nine years in various R&D, marketing, and sales and support positions at LogicVision. Burek received a MSc(EE) from the University of Manitoba in 1987.
PHIL BISHOP recently joined Pyxis Technology, Santa Clara, Calif., as president and CEO. He has worked for 17 years in the EDA industry, including time as CEO of Celoxica and in various senior management roles at Mentor Graphics Corp., Motorola, and Boeing. Bishop earned an MBA from the Fuqua School of Business at Duke University and holds computer and electrical engineering degrees from the University of Michigan.
WON-YOUNG JUNG is the CTO and founder of Nanno Solutions, Sunnyvale, Calif. He has spent 19 years in the process, T-CAD, and design automation industries with companies on both sides of the Pacific. His career includes research and managerial stints with LG Semiconductor, Aspec Technology, and Cadence Design Systems. Since 2004, Jung has been executive VP/CTO at Nanno Solutions. He's written 29 technical papers and holds 31 patents (with another pending) in the U.S., Japan, Germany, Taiwan, and Korea.
