Soft errors--which are induced by cosmic rays, alpha particles, and thermal neutrons--increasingly dominate IC reliability at nanometer geometries. Yet a new design platform from iRoC Technologies gives designers a way to accurately project the risks of soft errors in their designs.
The first entrant in iRoC's Soft Error Design Solution Platform, SoCFIT 1.0, helps fabless semiconductor and system-on-a-chip (SoC) houses get a handle on how soft errors impact their design. The tool analyzes an SoC's soft-error risk at full-chip and block level, providing insight into which blocks may be the major contributors to the overall soft-error rate (SER). It then enables tradeoff analyses between various design elements to meet SER targets.
SoCFIT fits into standard design flows by accepting Verilog gate-level netlists. Once designers close their timing and power budgets, the netlist is fed into SoCFIT, which analyzes it against soft-error models for the designers' chosen library and process. The models are validated by 3D simulations and via test structures on test chips for various technology nodes.
Based on the designers' constraints, SoCFIT outputs soft-error figures of merit. These are organized according to the designers' block hierarchy, including each memory element. After seeing what the SER is and which blocks are the prime culprits, designers can use tradeoff analyses to implement techniques such as redundancy, error-correction coding, or hardened cells to reduce the soft-error risk to acceptable levels.
SoCFIT will be available in the first quarter of 2005. Pricing starts at $10,000 for a single time-based license with generic industry models for 130 nm.
iRoC Technologies Corp.