Electronic Design

Design-Rule Checker Bets The Farm On Parallelism

Promising full-chip design-rule checking (DRC) for designs of any size and at any technology node in two hours or less, Magma's Quartz DRC is a key component of the company's recently announced Cobra 2005.03 release. The truly scalable physical verification tool, which is a result of Magma's acquisition of Mojave Design, achieves its speed by applying fine-grained parallelism across a standard network (or "farm") of heterogeneous Linux machines.

The tool's runtime is linearly scalable with the number of CPUs, which gives design teams the flexibility to choose the DRC runtimes that best fit their needs. "We've tested the tool with as many as 100 CPUs or more," said John Lee, general manager of Magma's Physical Verification Business Unit. "There appears to be no limit to the scalability."

Quartz DRC has been beta-tested with a number of semiconductor and fabless-design houses, including Broadcom, nVidia, and TSMC. All designs tested during the beta period ran in less than two hours with peak memory usage of up to 10 times less than other DRC tools. All runs completed within 32-bit hardware limits. The tool provided very accurate and efficient modeling of lithographic and chemical-mechanical polishing (CMP) effects that dominate manufacturability at 90 nm and below.

The DRC tool is integrated within Magma's Blast Fusion implementation environment, yet it can run in standalone mode within Cadence or Synopsys implementation environments. Quartz DRC is available now. Contact Magma directly for pricing information for time-based licenses.

Magma Design Automation

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