Design Verification System Debugs Millions Of Gates

June 10, 2002

In a single, scalable hardware and software environment, designers can verify from 2 million to 128 million ASIC gates using new models in the Palladium series of design verification systems. The latest configurations also support up to 64 Gbytes of memory and over 8000 physical I/Os for target system interfacing. Key to the system's cosimulation performance is a high-speed channel between the workstation and Palladium, which lowers interprocess latency and delivers 5× performance over the previous channel. Other new features include a standardized intellectual-property (IP) card form factor that interfaces physical IP cores within Palladium's IP chassis to designs for both simulation acceleration and in-circuit emulation. New configurations will be available in the third quarter of 2002 and can be obtained through the QuickCycles EXtended Access program, in which customers can have immediate remote access to company technology or on-site access on a pay-as-you-go basis. List prices start at $15,000/million gates/month. dm

Quickturn
www.quickturn.com; (408) 914-6000

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.