Electronic Design

Designers Pick EDA Favorites: Tools To Get It Right–Fast!

Engineers have a lot of positive things to say about the current state of the EDA industry, including some good ideas on how to improve tools.

When it comes to tools, every craftsman has his or her favorites. Cabinetmakers might single out their wood planes or stonecutters their chisels. And certain tools are essential to craftsmen—they'd be lost without them. In these times of multimillion-gate ASICs, circuit designers must have EDA tools to reach tapeout. They, too, have their favorites—tools that can be relied on to solve particularly thorny problems. Designers will often complain about their design tools, but they have got plenty of good things to say as well.

For most designers and design consultants, certain tools have turned into trusted allies. Some of them, such as design planners, have emerged as consequences of the times. If you're faced with physical implementation of millions of gates that make up dozens of intellectual-property (IP) blocks, a design methodology that encompasses floorplanning, silicon virtual prototyping, or physical synthesis has become mandatory.

For other designers, the latest generation of physical implementation tools has proved itself as a more sensible way of approaching the back-end flow. Interviews with personnel at foundries, ASIC manufacturers, and design consultants have turned up a broad spectrum of opinion as to what makes a tool or methodology a "favorite." Similarly, an informal online survey elicited feedback from a range of designers on everything from Spice to system-level design tools (see "Designers Sound Off Online," p. 56).

"My favorite tools save me time rather than cost me time," says Eric Decker, an independent design consultant in Mountain View, Calif. Generally, designers should look for tools that save them time. "There are certain tools you have to run to get a design that works, but those don't necessarily save you time."

"Every tool has its sweetspot, and so I don't say that there are bad or low-quality tools," says Hideki Yamada, EDA chief technologist with the System LSI Group at Toshiba America Electronic Components Inc. As do other large ASIC and system-on-a-chip design houses, Toshiba continually evaluates EDA tools to determine whether or not they're a good fit for its design methodologies. If Toshiba's EDA group finds that a particular tool's strength matches a need in the company's flow, it'll recommend it. Otherwise, it seeks alternatives.

The front end, or functional design portion, of the design process has seen much pressure in recent years to "clean up its act." In other words, it must pass better RTL code through synthesis and on to the back end, or physical implementation. This is approached in a number of ways, and designers cited several among their favorite tools.

"I like tools that prequalify a design before I run any simulations," says Decker. One example, and one that offers fast runtimes, is tried-and-true RTL linting. Linters examine RTL coding for proper style and syntax. They won't necessarily unearth problems in the code that cause implementation problems downstream, but they'll help catch other errors that might trip up synthesis. But linters are generally overlooked, Decker notes.

Also favoring code checkers is James Lee, president of the ASIC Group Inc., Fremont, Calif. "Code-checking and assertion-checking tools allow us to verify code without testbenches and simulation. They find bugs that would be annoying to find in simulation," says Lee.

In the past year, Lee and the ASIC Group have evaluated alternatives for ASIC synthesis and code-checking tools. "We now throw all new code through Real Intent's Verix property-checking tool before simulation and before signoff," says Lee. "I think it has helped us find bugs early."

Another way to approach RTL cleanup, but with an eye toward smoking out issues that will make implementation an endless loop of synthesis, placement, and routing iterations, is RTL rule checking. At Toshiba America Electronics Corp., RTL rule checking is an integral part of the front-end design cycle. In Toshiba's flow, when RTL handoff is called for, Toshiba's design-center engineers will rely on RTL rule checking to ensure that the code isn't harboring clocking or congestion problems.

"We use the Atrenta Spyglass RTL rule checkers as well as other similar tools," says Toshiba's Yamada. Toshiba uses the Atrenta tool with customized rule sets. "We have developed our own DFT (design-for-test) and clock-structure rules," he notes.

Toshiba also utilizes and has good success with Cadence's First Encounter for virtual prototyping. Using a gate-level netlist as input, First Encounter finds any rough spots in the design before moving on physical implementation. "With its high capacity, First Encounter can read in an entire netlist flat. It can do partitioning and initial placement so we can see whether we'll be able to achieve timing closure," says Yamada.

Proactive design auditing and validation is improving the throughput of design teams at Agere Systems, says J.C. Parker, technical manager of Agere's Hierarchical Design and Timing Solutions Group. Agere is implementing these audits through use of Atrenta's Spyglass rule checker. "We use a strong suite of both Agere-written design audits, as well as policies direct from Atrenta to validate design aspects that include clocking architectures, DFT insertion, RTL structure, timing constraints, and others," Parker explains. For Agere, these audits identify deficiencies early in the design flow that would halt or delay the effective execution of downstream processes.

At IBM, RTL rule checking is also in vogue. Aidan Kelly, manager of ASIC methodology at IBM Technology Group, Burlington, Vt., relates that IBM favors Tera Systems' TeraForm and Cadence's First Encounter for RTL rule checking and silicon virtual prototyping.

"What I like about both of these tools is their ability to tell us if assumptions about physical implementation are realizable. As an ASIC supplier, the ability to look at RTL and get good quality is very important to us," says Kelly. "What is key today is to examine details that will affect the design at 130 or 90 nm and try to see what can hurt you as early as possible." A generation or two ago, noise was most apt to be troublesome. But today, says Kelly, it's power.

First Encounter also figures in the flow at Agere Systems. According to Parker, Agere depends on First Encounter in the front end to help identify problems that will cause implementation issues. "First Encounter has proven an effective addition to the design flow for early prototype and planning. The speed of the tool enables rapid exploration of the design space to identify the optimal floorplan for timing and congestion," he says.

Design planning and virtual prototyping are important in the flow at LSI Logic as well. "It's important to quickly analyze and adjust a design in terms of RTL coding and architecture as it looks in the physical space," says Jeff Vanderlip, LSI Logic's director of tool and methodology marketing. LSI's philosophy is to enter implementation with RTL code and an architecture that's at least very good, if not optimal.

LSI Logic works with the Tera Systems tool, both for standard-cell ASICs and in the company's RapidWorx flow for its RapidChip structured ASIC products. Also in its RTL physical-analysis flow is Synopsys' Floorplan Compiler. "Data from the Tera Systems tools is used in Floorplan Compiler as a starting point," says Vanderlip. "Those tools complement each other, but it takes a lot of focus for us to interface them."

In the functional-verification arena, more designers are turning to assertion-based verification as it becomes better supported by EDA vendors. The emerging SystemVerilog language now provides support for assertion-based verification. Standards organization Accellera plans to unify its Property Specification Language (PSL) with SystemVerilog 3.1 assertions to produce PSL 1.1 while also synchronizing Accellera's Verilog analog/mixed-signal (Verilog A/M-S) standard with SystemVerilog syntax.

To Cliff Cummings, president of Sunburst Design Inc., Beaverton, Ore., SystemVerilog is the answer to the verification bottlenecks that continue to plague ASIC design. "Some of the vendors are starting to implement assertions that are very PSL-like," he says.

Cummings, whose company provides design consulting and SystemVerilog training, is quick to point out that few EDA vendors, if any, currently provide full support for Verilog 2001, never mind SystemVerilog. "But because SystemVerilog is fully backward-compatible, you can just start using any SystemVerilog features it might support now," he adds.

To reduce risk, many companies begin development of a complex circuit using FPGAs as the platform. Design consultants, who see lots of different design flows, report that the final implementation for a circuit design (FPGA or ASIC) can heavily influence design flows, particularly when it comes to simulation.

"People going right to an ASIC spend a lot more money on verification," says Tom Moxon, president of Moxon Design, Beaverton, Ore. "But in an FPGA flow, you can go right to prototyping and actually do incremental development in the lab, bringing up your algorithms on the hardware. That reduces a lot of the verification issues. There are fewer functional issues and more signal-integrity and design-rule issues as you migrate your FPGA to an ASIC."

In pure ASIC flows, Moxon often sees Synopsys' VCS used for simulation. In an FPGA-to-ASIC flow, though, he sees more of Mentor Graphics' ModelSim, which, he says, "is better supported on the FPGA side."

Often, Moxon says, implementing designs on FPGAs is a matter of stitching together disparate IP blocks when the inner workings of those blocks may not be so well known. "In those situations, there are two tools I really like. One is Mentor Graphics' HDL Designer, which helps you analyze how the IP is put together. The other is Hier Designs' PlanAhead tool. Using HDL Designer to analyze the IP and PlanAhead to do the hierarchical floorplanning and layout is a powerful combination," he says.

For FPGA synthesis, Moxon has seen more use of Mentor's Precision synthesis product. "Generally, for smaller, simpler circuits, the FPGA vendors' synthesis tools work okay," Moxon adds. "But I'll see up to a 15% performance gain by going to Mentor's Precision Synthesis or Synplicity's Synplify." The FPGA vendors' tools have difficulty with some Verilog and VHDL constructs, Moxon continues.

ASIC designers know that with the advent of process geometries below 130 nm, they'll eventually be forced to adopt physical synthesis. The current shift toward RTL rule checking and silicon virtual prototyping is more or less a stopgap measure that helps resolve physical issues before entering implementation. But some designers feel they can still get by with existing synthesis tools.

According to Steve Golson of Trilobyte Systems, Carlisle, Mass., ASIC designers shouldn't count out Synopsys' synthesis warhorse, Design Compiler, in the multimillion-gate age. "I've not had trouble with Design Compiler, even with designs as large as 1.5 million gates," says Golson, a consultant who specializes in synthesis.

Designs that large don't even have to be partitioned and can be run through the tool flat, Golson maintains. This may be a surprise to some who've become convinced that Design Compiler is out of steam. He believes it's still got some life left. "Synopsys has continually improved the tool over the years," he says.

On the implementation side, designers have their favorites as well. Foundries see all kinds of flows. According to Walter Ng, senior director of design solutions at Chartered Semiconductor, Milpitas, Calif., the dominant customer-owned-tooling (COT) design flows today are from Synopsys, Cadence, and Magma, in that order.

"Maybe its a matter of cost, or perhaps of wanting to hold a single EDA vendor accountable, but we see a trend among fabless semiconductor houses of seeing things as more of a flow," says Ng. "But we do see more users going with one particular vendor's flow."

Consultant Tom Moxon concurs with Ng. "All these things occur in cycles," he says. With the advent of Magma and Monterey Design Systems, Moxon believes, "We're at the cusp right now of the next cycle of integrated tools."

In its ASIC flow, Toshiba America Electronic Components employs Magma's Blast Fusion for timing closure implementation. "One of the benefits of using Blast Fusion is that we don't need to consider correlation," says Toshiba's Yamada. With its single unified database, Blast Fusion provides Toshiba with a very consistent flow and methodology, according to Yamada. "We attribute that largely to the consistency among their delay calculators and other analysis engines."

While more designers favor integrated flows these days, others still grapple with cobbled-together collections of point tools. For them, one issue is the explosion of file formats and side files that such flows generate. "One of the reasons Toshiba went with Magma was the fewer files that were generated," says Moxon.

In his consulting practice, Moxon is a fan of RunTime Design Automation's tools, which can help manage the interdependencies between point tools. More importantly, it manages the thousands of side files generated by point tools.

Consultants spend a great deal of time ironing out the inconsistencies between point tools. There's widespread agreement that true interoperability would make everyone's lives easier. "We need standards to move IP in and out," says IBM's Kelly. "Standards across the industry will help people solve the design problems. IBM is working on OpenAccess to standardize the models so tools can talk to one another."

OpenAccess, an industry initiative involving a standard design-data database and application programming interface (API), is being spearheaded by the Silicon Integration Initiative. Based largely on technology donations from Cadence, it offers one possibility for an industry-standard format that will allow tools to communicate with each other in a more seamless fashion. Another contender is Synopsys' Milky Way database.

LSI Logic built its RapidWorx flow for the RapidChip structured ASICs on the OpenAccess database and API. "What we like, want, and need are databases that are fully open to all vendors to develop on," says Vanderlip.

At Agere, inconsistency between tools hampers their interaction, even tools from the same vendor. "The core areas of inconsistency that we face today are related to the specification and measurement of gate-level timing and the interpretation and prevention of physical design-rule violations," says Parker. Agere minimizes these inconsistencies' impact by proactive analysis of design data for potential causes and removing or restricting the offending structure or component. "We continue to work with our key EDA suppliers to repair specific inconsistencies as they are encountered."

For Trilobyte's Golson, tool interoperability is a relative affair. "Companies like Cadence who tout integrated flows didn't develop all the tools in those flows anyway," he points out. "They bought those tools, inconsistencies and all." So, perhaps with the exception of truly integrated tool suites built around a common database, there will always be some interoperability issues.

Today's tools have plenty of room for improvement, especially with 100- and 90-nm silicon processes on the horizon and 65-nm processes on the drawing boards. "Where I see the most difficulty at 65 nm is synthesis," says Kelly. "The way we do it today, taking a snapshot of the design in gates, won't work. Synthesis has to be more intelligent about finding the optimal point to fulfill all parameters."

Yamada sees weaknesses in the test area. "We are working hard to reduce test cost," he says. Toshiba is evaluating design-for-manufacturability (DFM) technologies to help in this regard. "Another area we have to consider in testing is at-speed testing," Yamada continues. "Currently, clock frequencies are exceeding the ATE (automatic-test-equipment) frequencies. So we need a special test technique for at-speed test during manufacturing. This is something we are lagging on."

Another lagging area is IC-package co-design, particularly for high-pin-count and flip-chip devices. "The implications of the package design can no longer be ignored for high-frequency, high-signal-count designs," says Parker. "Nor can a complicated silicon design be completed without regard to the package concerns."

Agere relies on a suite of internally developed co-design tools in its production flow. While this flow is effective today, it could gain efficiency by simplifying the interface and improving the sharing of data between the package and silicon design tools.

"We are working closely with our core EDA partners to improve this interface, but a transition to a pure commercial solution is some time off," Parker notes.

Many designers see problems in the area of power analysis. "As we go to on-chip voltages below 1 V, I don't see a good answer for transient IR-drop analysis," says Kelly. "There's a lot of work left to be done to determine current signatures for pieces of IP and how currents affect timing when voltages are that low. As accurate as models are getting, that's still an area where the industry needs to focus."

Need More Information?



Cadence Design Systems


Hier Design

Magma Design Automation


Mentor Graphics

Monterey Design Systems

OpenAccess Initiative

Real Intent

Runtime Design Automation



Tenison EDA

Tera Systems

TAGS: Toshiba
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