Achieving timing closure in system-on-a-chip designs in a reasonable amount of time can be daunting. You can wait until you get to the block-level integration stage, but you'll probably have an easier time of it if the RTL designers of each block ironed out the timing issues. That's the idea behind InTime's Time Director, a tool that brings RTL timing analysis to the designer's desktop.
Time Director captures design intent at the block level as the RTL is being coded up. Static timing analysis is moved to the front of the design process, where it operates at RTL rather than waiting for a gate-level design representation. What results are easy edits of problem RTL and a quicker path to timing closure at both block and full-chip level.
With Time Director comes a full debug environment built around RTL timing, RTL schematics, and full hierarchy analysis combined with cross probing. It also provides block-level area estimates to help the design team plan for downstream packaging, data-flow, and floorplanning issues.
The tool easily integrates with existing synthesis and silicon virtual prototyping flows from Cadence, Magma, and Synopsys. It offers interfaces for standard outputs such as Synopsys-compatible constraints, LEF, DEF, and .lib.
Now in customer beta test, Time Director will ship this month. An annual time-based license costs $50,000.