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Development System Supports Million-Gate PLD Designs

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The latest release of the Quartus development software supports the firm’s APEX EP20K1000E programmable logic device, a 1 million usable-gate device that’s said to be the industry’s largest. Quartus 1999.06 delivers features that are required to support multi-million gate designs created for the APEX programmable logic architecture. Included are advanced compilation features, seamless integration with third-party EDA tools and an advanced verification environment that enables engineering organizations to efficiently conceive, optimize and verify multi-million gate designs. On a benchmark suite of more than 80 customer designs ranging from 1000 to 25,000 logic elements, the average timing-driven compilation time was less than 1 hour using 200-MHz Pentium-based computers.At the system’s heart is the nSTEP compiler, which includes CoreSyn, a technology that gives users the ability to analyze a given design and optimally implement blocks of logic (either look-up table logic, product term logic, or embedded system blocks) into the APEX MultiCore architecture. An advanced timing analysis tool with the capability to handle multi-clock and multi-cycle paths has been embedded into the nSTEP compiler to enhance timing-driven compilation. The nSTEP compiler is said to be the industry’s fastest timing-driven compiler, enabling users to get their designs ready and to market faster. For efficient transfer of information from tool to tool, the system uses NativeLink integration for seamless linking of information between the Quartus software and other EDA tools. The Quartus tools are part of all of the firm’s development tool subscription packages. They support most major OSs.

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