Electronic Design

DFM And Low-Power Design Will Dominate The Back End

Yield is on everyone's minds these days, particularly as 65-nm processes ramp up. Consequently, this year's big push in the implementation flow will be toward tools and methodologies that maximize yield and manufacturability. Overall, the IC implementation market continues to expand, even though the number of IC designers continues to dwindle (see the figure). A secondary thrust will concentrate on low-power design.

Design-for-manufacturability will no longer be a trendy buzzword, what with the first useful technologies emerging in 2006. Next year, several new tools will perturb a design with the goal of improving its production yield. Such technologies become useful only when applied with supported manufacturing data, and the results are measurable.

In addition, the other half of the equation will begin to emerge: design-aware manufacturing. Manufacturers will begin using technologies that can take in information about a design and use it to improve the design's parametric yield. For example, identifying a design's critical signal paths to the manufacturer will become important. Manufacturers will begin to process the critical features of a design differently from non-critical design features. But the benefits will be driven, or limited, by the amount and quality of the data shared between designers and fabs.

The push for a design-for-manufacturing (DFM) flow must begin even before implementation. It's in the synthesis stage that designers must meet timing, area, power, and test goals within the shortest possible time. To address this need, we've seen new advances in synthesis, with more to come in 2006. New topographical technology, for example, helps designers accurately predict post-layout timing and area without the need for wireload model-based timing approximation.

True DFM will emerge both for the custom/analog design and SoC/digital design environments. A comprehensive approach will be required as DFM, signal integrity, voltage drop, thermal issues, timing, and low-power optimizations all intertwine (see "In Quest Of 'Homo Futurus' Physical Design," p. 100). Ultimately, an integrated back-end platform-will incorporate technologies that let designers anticipate-the effect on chip layout of resolution enhancement technology (RET), as well as automated yield analysis and enhancement of designs.

RET helped close the design-to-manufacturing gap. Other technologies are following suit, such as statistical yield analysis. Lithography-aware technology will move up into the design-creation flow, with tools that enable cells to be designed as not just DRC-clean, but lithography-clean. This will ensure printability of cells over the process window. Next, lithography-friendly design tools will ensure cell performance.

EDA companies and chip designers must team up to reduce chip power consumption. In particular, the ability to switch off power or change voltage for some of the chip's modules is important. Moving into 2006, RTL-to-GDSII implementation flows will become more complex since there will be multiple power lines and many voltage islands on-chip.

Sub-threshold leakage power is increasing exponentially with each new process generation—90-nm leakage is five times worse than 130-nm leakage. Gate leakage is worsening even faster. We'll see technologies allowing exploration of various leakage-control techniques in isolated areas of a design. Power gating—disconnecting the power supply from logic to reduce leakage—is certain to be a key weapon in containing leakage. The next generation of tools will be able to automate power gating, replacing all non-power-gated cells with the equivalent power-gated versions, and inserting switches to manage power.

Given the power-dominated challenges of portable designs, designers will move to tightly integrated design platforms. Some are standardizing on full-chip flows that support power-network synthesis and power-network analysis during design planning, as well as power network analysis and sign-off.

On the routing side, the X Architecture will continue to gain momentum as manufacturability concerns fritter away. Look for more high-end designs to exploit the architecture to increase speed and reduce manufacturing costs.

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