Electronic Design
 Digital Implementation Flow Readied For 28-nm Silicon

Digital Implementation Flow Readied For 28-nm Silicon

The consumer electronics market largely determines the demand for high-end systems-on-a-chip (SoCs). Applications such as cloud computing are driving those demands higher. The problem for design teams is that there’s a gap between what they’re attempting to achieve in terms of device complexity and density and what EDA tools can provide.

In its Encounter Digital Implementation System (EDI) 9.1, Cadence Design Systems aims to raise the bar in terms of what a modern implementation flow can deliver. Most notably, EDI 9.1 enables the creation of designs that are two to three times larger than its predecessor could achieve through a hierarchical, high-capacity prototyping flow.

At ultra-deep-submicron process nodes, design teams need ways to avoid silicon respins. At the 32- and 28-nm nodes, the total cost for large designs is expected to approach $100 million. Missing a market window by six months for a respin could mean a potential loss of $5 billion in profits.

EDI System 9.1 is intended to help designers avoid these missteps in several ways. For one, its floorplanning and prototyping flow allows automatic and concurrent examination of hundreds of design variables. This way, designers can quickly find an optimal architecture for their SoC.

Whereas traditional flows require repeated iterations to arrive at design signoff, EDI System 9.1 provides a methodology that is geared for coping with the enormous amounts of data required for physical design at 32 and 28 nm. This forces a move from flat design methodologies to a hierarchical approach in which designs are partitioned and implemented as blocks. The complete design is then assembled hierarchically at chip level.

According to Rahul Deokar, product marketing director for the Encounter platform, current flows are inadequate for this task. “With today’s flows, you have to partition the design into smaller blocks than needed to facilitate place and route,” says Deokar. “There is no convergence between process steps. This leads to long cycles of endless iterations and an explosion in design-cycle length.”

In contrast, Cadence calls EDI System 9.1 a next-generation SoC implementation system (see the figure). It’s intended to streamline and tightly integrate floorplanning and prototyping with place and route and signoff. It offers very high capacity for design exploration fueled by Cadence’s data abstraction modeling. The system performs automated floorplan synthesis with concurrent cell and macro placement. Tight links with chipestimate.com provide early architecture planning with physical awareness.

The system also improves design predictability and convergence through fully integrated signoff analysis. “We already had timing, signal integrity, and power analysis integrated into Encounter,” says Deokar. “We’ve augmented that with silicon-accurate turbo extraction.” The result, says Deokar, is a flow with virtually no iterations and greatly improved quality of results (QoR).

Another benefit is the speedup of late-stage incremental engineering change orders (ECOs). “Because the extraction engine correlates to closely to signoff, there’s a huge runtime benefit,” says Deokar.

Finally, in terms of design for manufacturing (DFM), EDI System 9.1 supports all 32- and 28-nm requirements for routing and design rule checking (DRC). “The communications between the router and signoff tools that help at 65 and 45 nm are now a bottleneck,” says Deokar. “At 32 and 28 nm, designers need a self-healing DFM flow, and that’s what we have here.”

Cadence’s Encounter DFM lithography hotspot fixing, incorporated within EDI System 9.1, screens the design during routing for areas that could become hotspots in silicon. It then automatically finds and repairs these areas.

Cadence Design Systems

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