EE Product News

Dramatic Shortening Of Design Times Claimed For ASICs

product pic

The CL10KA family of no-NRE ASICs are said to dramatically shorten design time and increase design flexibility in cost-sensitive applications. The CL10KA ASICs are functionally and I/O identical to Altera's FLEX 10KA user-programmable FPGAs, which can be used to prototype and debug CL10KA ASIC designs. The ASICs are based on the firm's vertical link-configured ASIC technology from which extremely small dice having full architectural compatibility with Altera FPGAs can be produced. In addition, designers can implement high-level, reusable intellectual property (IP) cores to simplify the design process and short design time. Any IP core that is optimized for the Altera 10KA architecture will function identically in the CL10KA architecture. Because the Altera FLEX 10KA FPGAs are in-system reconfigurable, designers can quickly prototype and test their ASIC designs in the actual hardware configuration without incurring any of the costs normally associated with ASIC prototyping. The CL10K50V is the first device in the family and is a 3.3V, 50,000-gate device with 20,480 bits of embedded SRAM. This device is functionally identical to the Altera EPF10K50V, which is the prototyping medium for the CL10K50V. Clear Logic delivers samples of the configured CL10KA ASICs within two weeks of receiving the users design bit stream.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.