As ASIC, ASSP, and SoC designers squint down the road past 100-nm feature sizes, they can make out a world in which their tried-and-true assumptions about the design process are severely challenged. For one, the process will begin above RTL with architectural exploration and refinement. For another, power issues will predominate in two ways--reducing consumption and eliminating power-related chip failures.
To answer the call for technology support, the EDA industry has come through with a new barrage of tools and methodologies. On the electronic-system-level (ESL) side, a wave of startups is hooking up with EDA giants to develop new flows that make design above RTL a reality. Power issues also are getting addressed in implementation and post-layout analysis. Both of these areas, which represent keys to successful silicon at ultra-deep submicron geometries, drew a great deal of attention at this year's Design Automation Conference (see "The 41st DAC: Optimists Ruled The Day," p. 64).
In the ESL realm, activity abounds as vendors, IP providers, and consortia strive toward a complete flow from the algorithmic level to RTL. Cadence and CoWare joined forces to create what they're calling a seamless flow from ESL through verification for complex SoC designs. Representing a major milestone on the strategic alliance roadmap for the two companies, the flow follows the integration of CoWare's SystemC-based ConvergenSC SoC design tools and ConvergenSC Model Library and Cadence's Incisive verification platform.
With the Cadence/CoWare flow, designers can rapidly explore design variations in ConvergenSC and settle on an optimal architecture. The architecture is validated using SystemC transaction-level models (TLMs), which can be simulated up to 10,000 times faster than RTL. Then the SystemC model becomes a functional virtual prototype with an embedded software testbench. That model is used by the Incisive platform so that verification engineers can verify the RTL implementation at over 100 times the performance of an all-RTL system.
Synopsys and Virtio teamed up on an ESL verification approach that connects SoC hardware and software-development flows. The collaboration integrates Virtio's high-speed software models, including models for popular embedded processors, with Synopsys' Discovery verification platform.
Basically, software developers need a hardware prototype, as well as speedy simulation and debug. Virtio's technology enables designers to create a virtual hardware platform for debugging software. With execution speeds of over 20 MIPS/GHz, Virtio's technology delivers the performance that SoC designers require for pre-silicon software development. The integration of Virtio's platform technology with Synopsys' VCS RTL simulator and Vera testbench-automation tool ensures that the virtual software-platform models, architecture models, and RTL models stay mutually consistent throughout the development cycle. That solves a major concern for designers on both sides of the fence, and it provides an opportunity to reduce the overall SoC development cycle by six to nine months.
SpiraTech, a U.K.-based startup, garnered recognition with its Cohesive ESL-to-RTL flow. Many of today's simulation environments support SystemC, Verilog, and VHDL simultaneously, but often they support interaction at a single level of abstraction, usually the cycle-accurate level. The Cohesive tools hurdle this barrier by giving visibility to activity at all levels of abstraction. Products include an ESL and RTL graphical debugger, a system performance profiler, a multilevel protocol checker, a library of full-spectrum abstraction adapters for industry-standard buses and protocols, and a generation tool that helps create adapters for proprietary and less-common interfaces.
SYNTHESIS ABOVE RTL
Synthesis for SystemC is a red hot topic these days. Celoxica recently entered the fray with its Agility Compiler, which synthesizes SystemC directly to high-density FPGA and programmable SoC logic. The tool takes in SystemC and produces optimized EDIF netlists for high-density programmable-logic devices fom Actel, Altera, and Xilinx (Fig. 1). It also generates VHDL and Verilog RTL output to support SoC synthesis tools.
The compiler lets FPGA and programmable SoC designers using SystemC maintain the C level of abstraction throughout the entire SystemC design process. It brings much faster simulation speeds than RTL, and the entire system design can be verified with the same testbench at all stages of the process.
Another new entrant in the SystemC synthesis arena is Mentor Graphics' CatapultC, which is distinguished by its ability to keep source code independent from the hardware interface. It enables designers to quickly analyze performance tradeoffs between, say, single-port versus dual-port memory, with the resulting hardware tuned to the interface bandwidth.
IP creation and management is a critical capability in an ESL flow. Synopsys' coreAssembler tool is now generally available to DesignWare IP customers. It's part of a full set of IP reuse tools that includes coreBuilder for IP block packaging and coreConsultant for configuration and implementation of individual IP blocks. The coreAssembler assembles and configures IP-based subsystems and complete SoCs.
Similarly, IP evaluation is of paramount importance to an ESL flow. Tenison EDA's VTOC Export makes for secure and licensable IP distribution of C++ models based on the company's VTOC Generate tool. VTOC Generate creates fast, cycle-accurate executable models in SystemC and C++ from existing IP hardware models written in RTL. VTOC Export then provides an embedded licensing scheme that enables users to control distribution of the secure models to customers, partners, or internal organizations.
On the IP standards front, the SPIRIT (Structure for Packaging, Integrating and Re-using IP within Tool flows) Consortium released a proposed SPIRIT 1.0 standard to its membership for review. After extensive validation, Version 1.0 is expected to be released publicly early in the fourth quarter of 2004. The standard will support multiple tool flows and IP libraries.
The proposed SPIRIT 1.0 specification offers a complete method for RTL SoC design encapsulation. It will permit automated IP integration, as well as interoperability of configurable and nonconfigurable IP with multiple toolsets. By enabling a standard machine- and human-readable description of IP block structure and general attributes in XML (eXtensible Markup Language), SPIRIT-compliant IP will be able to flow smoothly into EDA tools that support the SPIRIT format.
When industry groups work together toward common goals, the results can at times be quite exemplary. For instance, the Open SystemC Initiative (OSCI) and Open Core Protocol International Partnership (OCP-IP) together created an interoperable modeling infrastructure for transaction-level modeling (TLM) with SystemC. OCP-IP, which is dedicated to creating a common standard for IP core interfaces, chose System C as a leading platform for delivering transaction-level models of OCP-IP-based communication channels. Meanwhile, the Transaction-Level Modeling Working Group of OSCI is defining an application programming interface (API) for transaction-level communication.
The two groups came together to ensure the OCP-IP TLMs can be built in the future on top of the standard OSCI APIs. By teaming up, the groups hope to eliminate any possibility of competing standards. OSCI plans to provide generic TLM transport functionality, while OCP-IP foresees using that functionality to implement models of its specific communication channels.
POWERING UP* Power predominates the thoughts of many designers as they contemplate the shift to subnanometer process technologies. There's good reason for this: Technology scaling and resulting soaring gate counts carry serious implications in terms of power. There will be increased leakage and dynamic power, as well as decreased chip reliability due to voltage-drop and electromigration effects.
If a problem is on the mind of designers, you can bet it's on the mind of EDA vendors. Synopsys' Galaxy Power epitomizes some of the industry offerings for optimizing power in 90-nm IC designs. It delivers up to a 2× leakage-power reduction without impacting the implementation flow. On top of that, it offers new capabilities for standby-mode (state-retention) designs and support for multithreshold designs.
For low power, Galaxy Power performs power-grid synthesis and power optimization with support for automatic hierarchical clock gating, multivoltage designs, multithreshold leakage, and state-retention power gating. Vector-free power analysis and sign-off-level power integrity are also part of the package.
Magma Design Automation also integrated power optimization and management into its RTL-to-GDSII flow. Blast Power is a forthcoming option to Magma's Blast Create and Blast Fusion APX methodology, which includes embedded power, timing, and rail analysis as well as power-minimization techniques. With Blast Power, Magma users can create power-vs.-timing and power-vs.-area tradeoffs throughout the flow without exporting design data outside of the Magma system.
Blast Power provides power-aware synthesis, automatic power-grid synthesis, and leakage-power optimization using multiple-threshold voltage libraries. Like Galaxy Power, it supports designs via multiple voltage domains and provides for power-aware placement and optimization.
Determining the severity of power-integrity issues is, in itself, vexing. Sigrity's XcitePI tool performs dynamic simulation of the full-chip power-grid structure, with package effects, to get a handle on the extent of power problems (Fig. 2).
Typically, a power grid's resistive, capacitive, and limited inductive coupling effects are dealt with using lumped off-chip RLC models. XcitePI instead analyzes the power grid with distributed electromagnetic-field propagation effects of the package. It also considers the capacitive and inductive coupling between all conductors in the chip's power grid.
Often, noise propagates to other areas of a chip through the package power and ground structures, rather than the power grid. Lumped off-chip RLC models can't readily model such effects. XcitePI performs transient analysis of the IC power grid while dynamically simulating electromagnetic fields in the package power and ground planes.
Power issues are also a concern for silicon foundries. Taiwan Semiconductor Manufacturing Co. (TSMC) has rolled out its Reference Flow 5.0. It's viewed as the industry's first reference flow providing critical power closure and integrated chip-to-package design for nanometer SoCs. The flow is built around tools such as Cadence Design Systems' Encounter digital-IC design platform and Synopsys' Galaxy design platform. It includes specialty tools from Mentor, Apache Design Solutions, Atrenta, and Optimal.
Reference Flow 5.0 addresses dynamic power optimization, leakage power optimization, and static and dynamic IR-drop final verification. When implementing SoCs in TSMC's Nexsys 90-nm technology, users will be able to insert level-shift cells and isolation cells. Thus, blocks of circuits can run at different voltages, and circuit leakage between power domains is prevented.
On the power-integrity side, TSMC chose Apache's Redhawk-SDL power verification suite, which incorporates the effects of simultaneous switching (core, memory, and I/O), intrinsic and intentional decoupling capacitors, and on-chip and package inductive effects. Static-only approaches largely neglect all of these.
Atrenta's SpyGlass LP (for low power) made it into the TSMC flow for its ability to enforce good low-power design practices at RTL. It addresses architectural-level, low-power design techniques such as the use of voltage and power domains that have maximum impact on power consumption. Its set of techniques for use early in the SoC design cycle ensures automatic checking and generation of interface logic.
TSMC's chip-to-package integration flow also uses Atrenta's SpyGlass ERC. It validates a gate-level netlist for a wide range of electrical rules and reports critical rule violations. SpyGlass ERC takes in Synopsys Liberty format (.lib) files along with a netlist to seek out problems like overloaded drivers, undesired clock interactions, delay-time dependent circuits, and library-specific errors. The idea is to achieve a clean netlist handoff to the physical implementation phase of the process.
Also key to TSMC's power-closure plans for 90-nm designs are several tools from Optimal Corp. The company's PowerGrid-DC addresses IR drop, current density, and Spice netlists. The PakSi-E and SIDEA tools extract package parasitics and generate timing data in Standard Delay Format (SDF).
In the past, the current entering an IC was relatively low, so the resistance created by the package (IR drop) was easily modeled and accounted for through package and lead selection. But in today's design environment, currents are very high and package IR drops can be stiff enough to cause havoc in a 1-V design. Thus, designers must ensure that power distribution is sufficient.
The methodology used in TSMC's Reference Flow 5.0 for power closure uses Optimal's PowerGrid-DC to create an equivalent resistive Spice netlist among the solder bumps (or bond wires) and solder balls (Fig. 3). The netlist is imported as a loading condition into third-party tools to perform IR-drop analysis. Then the interaction between chip and package is accounted for automatically.
Due to space constraints, signal traces in packages tend to have multiple lengths. Such differences must be compensated for on pc boards. Therefore, an automated flow is needed to quantify the timing delay from the I/O circuitry to the package pins for proper trace compensation on the board.