Electronic Design

EDA’s Next Step: System-Level Design Automation

 

There’s little doubt that electronic design is undergoing a new wave of major transitions. Consumers’ insatiable demand for more capabilities at lower power and cost is driving the need for hardware and software development optimizations through all of the links of the electronic design chain, namely intellectual property (IP) providers, semiconductor providers, and system houses.

Without productivity improvements in design technologies, it would have long ago become impossible to design electronic products within timing, cost, and power constraints. According to the 2009 edition of the International Technology Roadmap for Semiconductors (ITRS), hardware design productivity had to be improved through automation more than 18-fold from 2001 to 2011 to keep up with growing complexity. During the same period, software design productivity more than doubled.

To keep up with the increased complexity of electronic developments over the next 10 years, automation needs to provide a more than 26-fold improvement on the hardware side and an almost 50-fold improvement for software. Clearly, the focus of design technology improvements has shifted from hardware to combinations of hardware and software.

From Yesterday To Today
In the past, productivity improvements using automation have been focused primarily on hardware. Increased chip complexity and automation have led designers to raise the levels of abstraction at which the design entry happens. Design entry, which used to occur at the layout level, later moved up to transistors. The creation of the layout then became a matter of automation, and the industry went from transistor schematics to the gate level and automated the flow from there. From gates, we then went to the register transfer level (RTL), and logic synthesis helped to automate the flow from there.

Since most of the design entry moved to RTL, the industry has been in search of the next level of abstraction. What today is called transaction level has been standardized with SystemC’s TLM-2.0 application programming interfaces (APIs) for simulation interoperability. In moving beyond RTL, however, the design entry point from which the industry automates is not all that matters.

The reuse of large blocks like processors and interface IP, as well as methodology improvements for verification, has already greatly contributed to productivity improvements. Chip development teams need best-in-class simulation and verification technologies combined with methodologies to be successful with their designs at RTL today.

In addition, they need access to off-the shelf IP for processors, peripherals, mixed-signal IP, and connectivity IP. Furthermore, at RTL, they need the ability to integrate IP into designs and verify its correctness in the context of the system in which it resides—including software.

System-Level Design
Starting from this base, the industry has embarked on the route toward system-level design. Various pieces of the puzzle are well known, and three basic areas for productivity improvements are clear.

First, developers need best-in-class solutions for creating and optimizing blocks, efficiently driving ideas for subsystems into implementation. In today’s world, this is no longer a hardware-only task, and the role of hardware itself, while important, is shrinking. When contemplating a subsystem, a developer has three basic implementation options: software, hardware, and a mix of hardware and software.

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Today, most of the actual coding of the hardware piece is still done at RTL for hardware and with C/C++ for software. On the hardware side, high-level synthesis from C or C++ has made some inroads in digital signal processing applications for which the optimization of loops is crucial.

With verification at RTL being an unbounded problem, the need for abstraction has become clear here as well. Developers strive toward verification at higher levels of abstraction and automation from there.

On the software side, model-based design can help contribute to the required 50-fold productivity improvement in the next 10 years. Just like high-level synthesis for hardware, automated code generation from high-level models increased productivity in software development.

For the grey zone between hardware and software, the efficient creation of application-specific instruction processors (ASIPs) and dedicated hardware accelerators for processors has become an important element. Automation in this domain will significantly improve productivity going forward.

The second need is the enabling of the best system-on-a-chip (SoC) architecture. Complexity has simply grown too much, and today’s average of approximately 40 blocks per chip will easily double over the next five years. The on-chip interconnect fabrics have become so complex that they easily exceed the capabilities of even the best system architects.

Automation in this domain, such as being able to simulate and efficiently explore all required scenarios of a SoC and then appropriately configure the interconnect fabric, will be crucial. Different steps are required here.

Developers start with architecture design using trace-based analysis and optimization. They then continue toward architecture validation using accurate processor models or traces derived from less accurate simulation or hardware prototypes. Regardless of the method used, going to implementation without proper architecture analysis has simply become too risky given both current and future design complexity.

While the first need essentially calls for automating block and IP creation, the second calls for the automation of block and IP integration. The third need integrates both, at both pre-RTL and RTL. It is about substantially accelerating and optimizing the development of software in the context of hardware.

Virtual Prototyping
Recent surveys show that even today, often more than 50% of the actual project effort is spent on software. This trend will only become more prominent going forward. For the purpose of enabling early and efficient software development, prototyping is the right answer. Recent surveys by VDC Research show that more than 70% of projects already use FPGA prototyping.

Significant advances can be made here with automation to increase turnaround time and debugging. As a complementary method for accelerating software development, virtual prototyping is experiencing greater adoption. The same surveys also show that more than 40% of projects plan to employ virtual prototyping, a trend that is expected to increase as design teams try to advance software development to points in a project at which RTL is not even available yet.

Virtual prototyping is where the next level of design entry for block implementation and block integration meets the software world. In an ideal scenario, the transaction-level models can drive virtual prototypes for software development and verification as well as the automated implementation of new chip content, such as blocks that are not yet available as reusable IP. With further automation and integration of block creation flows either using or creating transaction-level models for virtual prototypes, even greater productivity enhancements can be expected.

What’s Next
The challenges are clear. To continue to satisfy consumer demand for semiconductor-driven content, automation must provide a greater than 19-fold improvement on the hardware side and a nearly 50-fold improvement for software. The pieces of the puzzle as described are apparent and the puzzle itself—integrating it to provide the most productivity improvements—is what the industry is tackling. Working from a solid base of IP at RTL and best-in-class simulation and verification technologies will enable a transition to the natural next step: system-level design automation.

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