Electronic design automation (EDA) tools are becoming vastly more complex each day. From my vantage point as an editor, I've seen wave after wave of increasingly powerful tools—from physical synthesis tools to SoC design suites to IC floorplanners—make their way to market. The user environments and design languages and processes change constantly. Editors often find the flood of information on new tools bewildering. It can't be much different for the practicing design engineer.
Consider the fact that every time a design project gets launched, designers must undertake a certain amount of due diligence with regard to EDA tools. Some tools and processes used on the last project will work on the next one, while others won't. What new tools will you need? Which of your old tools require upgrades?
If you were engaged for, say, the last year on an all-consuming design project, the first thing you did when you assembled your team and design tools was freeze your tool set. Now you have sent the design off for fabrication and you can come up for air. Guess what? Your tool vendor has already released a revision of the tools you used. There are new features and maybe a new interface. You have to get started on the next generation of your chips. It's not quite like starting over, but you have homework to do. It's almost impossible for design engineers to keep up with the changes made in the EDA marketplace.
According to Mike Baird, president of Willamette HDL Inc., a company based in Beaverton, Ore., that provides services and products related to language-based hardware design, it's even tougher for new engineers coming into the workforce from colleges and universities. "We generally find that new engineers entering the engineering community aren't trained well enough in either design languages or the use of tools to be productive," Baird says. Typically, larger OEMs might send new engineers first to a class on Verilog or VHDL and then to another class to learn the basics of synthesis tools from a vendor, such as Synopsys. In Baird's experience, it can take up to 30 days for a new engineer to gain the necessary language fluency to generate good code.
So, what options are available for designers hoping to keep on top of the EDA scene? Obviously, we at Electronic Design intend to stay up to date on the latest design tools, languages, and methodologies, and pass our knowledge on to you. Plus, training is available from Willamette HDL. The EDA vendors offer training in their own tools and have some traveling roadshows, Baird explains, but sometimes these lack good hands-on training for the designers.
Willamette HDL also creates computer-based training packages for vendors that are shipped to users along with the tool. The packages are an interactive, self-paced type of training that runs along with the tool in question. The tool vendors like this kind of approach because it can help get people started and it takes some pressure off of their field engineers.
Moreover, technical sessions are given at the various EDA-related industry conferences, such as the Design Automation Conference (June 18-22, Las Vegas, Nev.). The recent Design, Automation, and Test in Europe (DATE) conference ran several EDA-related tutorials, too. Watch for a new conference that will be tailored to the educational needs of EDA tool users. Called EDA: Front-to-Back (Sept. 24-26, Santa Clara Convention Center, Calif.), it will be a unique combination of technical conference and test-drive showcases for tool vendors. More information can be found at www.edafronttoback.com.