Electronic Design

EDA Tool Update

The OpenAccess application programming interface and database has seen another successful port. Cadence's Virtuoso Chip Editor chip finisher, which takes ICs through the final stage of design implementation, exploits the OpenAccess interface to eliminate a data logjam between Cadence's SoC Encounter design suite and Virtuoso. For details, see www.cadence.com.

Verisity and 0-In Design Automation are collaborating to report integrated verification coverage metrics to their customers. The coverage information available in Verisity's Specman Elite testbench automation tool will include both native functional coverage metrics and the structural coverage metrics from 0-In's CheckerWare assertion checkers and monitors. Visit www.0-in.com and www.verisity.com.

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