Designs are moving aggressively toward 130 nanometers (nm). Just on the horizon lie new technologies at 100 nm. Given these small geometries, three fundamental barriers must be overcome to improve the turn-around time of large system-on-a-chip (SoC) designs.
First, low-power/low-voltage processes are necessary to meet the strict battery-life requirements of portable devices: the cheap package and rack-size limits of consumer set-top-box and audio-video equipment, as well as ceramic package and grid-drop limits of high-speed processors. What companies are building these new flows?
Also, nanometer electrical design issues, such as coupling delay, glitch, electromigration, inductive interference, and voltage drop, require a concurrent design approach that's only possible when built on an analysis platform. SoC design sizes force next-generation engineering teams into hierarchical methods as part of a natural reaction to design complexity. Where are the new analysis platforms to provide better answers?
Finally, new processes like copper metallization for wires and silicon germanium (SiGe) for transistors need to reflect the changes in interconnect and device physics. The switch to copper metallization brings inductance forward as a design issue at higher frequencies. Copper has lower resistance and better electromigration attributes than aluminum. Lower resistance means faster chips, which, in turn, change the characteristic impedance equation from resistive to inductive (Z = R + jω × L).
New transistor materials, including SiGe, operate at higher cutoff frequencies, bringing high-speed performance into the SoC world. SiGe deposits easily on a standard CMOS process, forming a platform for mixing high-speed analog and digital elements together on one substrate. Better integration is achieved. But it comes at the cost of understanding the high-speed device parasitics and the critical interface interference between the analog and digital parts of the design. Who is working to model these new process effects?
EDA software buyers claim that they're too busy to evaluate new software from the numerous suppliers. Yet, most of these buyers continue purchasing a lot of recycled, repackaged software. Instead of streamlining their own evaluation process, or managing the supply chain with smaller purchases, they negotiate large deals with existing suppliers. The deals allow them to substitute aging products for new products. Although this offers them some protection against obsolescence, it restricts the flow of new innovative software into their own design flows.
Many EDA tool buyers believe that tool integration will solve their productivity problems. Experience brings productivity, but experienced designers and design-tool users are scarce. Although EDA vendors have responded with special design consulting services, tools must get smarter too. This has less to do with integration than with innovation. Integration is a very noble goal, but it has frequently been used to restrict competition. So a balance must be struck. EDA buyers are in the best position to encourage both integration and innovation because of the way that they manage the supply side of their business.
The critical concept in smart tool construction is the combination of concurrent analysis with concurrent synthesis. Some have called this a "golden" analysis tool. As technology drives toward 100 nm, designers face the confluence of electrical issues. Concurrent analysis is necessary for signal interfaces created by charge-based and magnetic-based aggressive sources; power stress created by higher switching speeds; greater leakage as a percentage of total power consumed; and the dependence of each on the others. These effects must all be detected for successful design. Smart tools can do this concurrently.
Once analyzed, these nano-effects require concurrent synthesis to correct the effect because each detected and corrected problem will introduce other potential problems. Successful design convergence will then require the concurrent synthesis of these choices and their implications, including the analysis of each cost function to determine the best tradeoffs. Widening the space between wires to reduce coupling can increase loop inductance by increasing the area of the current return path. Inserting shielding to eliminate noise will reduce routing resources and increase metallization costs and area. Smart tools can make these tradeoffs concurrently.
In nanometer design, the industry can't rely on the recycled ideas and merged solutions. The time has come to pass the torch to a new generation of providers, born in the deep-sub-micron era, and dedicated to producing a better solution. Look carefully for real innovation rather than recycled, repackaged software approaches. Most importantly, manage your buying process to get the most out of the suppliers that are willing to produce innovations in design software.