Today's nanometer era demands new chip-design approaches that consider manufacturing effects, as well as unprecedented levels of open collaboration throughout the silicon design chain. This year will be pivotal for the revolutionary new X Architecture and for design-to-manufacturing collaboration in general.
The X Architecture is based on a simple but powerful idea: The shortest distance between two points is a straight line. It represents a new way of orienting a chip's maze of microscopic wires using both diagonal pathways and the traditional right-angle, or "Manhattan" configuration. By enabling designs with 20% less total wire length and 30% fewer vias, it provides simultaneous benefits in terms of chip performance, area, power consumption, and cost.
Most excitingly, these benefits are realized without tradeoffs. Traditionally, performance increases came at the expense of area or power consumption. With the X Architecture, a design's performance can increase while its area and power specs are maintained or improved.
In June 2001, when the X Architecture first debuted, the biggest questions centered around its effect on downstream manufacturing, including photomask production, lithography, and manufacturing design rules. To address these questions, a group of leading companies from the semiconductor industry launched an initiative to accelerate the availability of the X Architecture. The X Initiative established a roadmap for bringing the X Architecture to production and created a foundation for collaboration to execute on that roadmap.
In October 2001, X Initiative member DuPont Photomasks revealed that it had created the world's first X Architecture photomask in collaboration with other X Initiative members. This experiment determined that existing photomask equipment could be employed to create X Architecture masks and that the cost of masks for the X Architecture was comparable to those of Manhattan designs.
ASML announced, in April 2002, that it had produced proof-of-concept wafer exposures of diagonally oriented interconnects based on 180-nm design rules. This confirmed that existing standard lithography solutions work for X Architecture structures.
In December 2002, Nikon Corp., in cooperation with other members, validated lithography readiness at 130 nm. In March 2003, STMicroelectronics presented the first silicon results: a 130-nm X Architecture design-rule test chip, establishing design rules for the X Architecture equivalent to those for Manhattan designs.
In June, Applied Materials announced a similarly successful design-rule test chip at the 90-nm process node. In October, X Initiative cosponsor Toshiba Corp. announced that it had completed the X Initiative's pre-production roadmap by producing the first functional silicon for the X Architecture at the 90-nm process node.
With the pre-production roadmap complete, this year will see the first production chips for the X Architecture. The X Architecture will be an attractive design-implementation option for those companies developing high-volume, high-performance, and/or low-power chips. Starting in 2004, the checklist for the design engineer will include not only process node (130 nm or 90 nm) and materials (copper, low-k, SOI), but also architecture (X Architecture or Manhattan).
The electronics roadmap for 2004 and beyond calls for more industry collaboration as technical problems get harder and the economic risks greater. To that end, the X Initiative has become a model for design-to-manufacturing collaboration. All of the X Initiative member companies, now a total of nearly 40, stand to benefit from their early collaboration by being able to offer optimized solutions for this new paradigm just as the market develops.