Electronic Design

Eighth-Generation Accelerator/Emulator Takes On 256 Mgates

More capacity in a smaller box—that sums up the Incisive Palladium II, Cadence's eighth-generation hardware acceleration/emulation system. At twice the speed and capacity of the first-generation Palladium system and just one-third of its size, the Palladium II hits a high-water mark by reaching the 256-Mgate capacity level.

Building on Cadence's processor-based accelerator architecture, the Palladium II is based on silicon with an effective gate length of 70 nm. The system's multichip-module (MCM) processors carry two ASICs, each of which contains 1536 processors. The MCMs also carry 128 Mbytes of memory with 2-ns access times. The result is runtime performance of better than 1 MHz and compile times of 10 million to 30 million gates/hour. With a maximum of up to 61,440 I/Os, Palladium II enables verification of a full system or multiple chips running in parallel.

The system's multiuser mode supports up to 32 users independently running both in-circuit emulation and simulation acceleration. With this optional feature, multiple users can gain access to the system from different sites as well as verify multiple pieces of their hardware and software. Palladium II also leverages the Incisive XE verification environment, which features support for transaction-based verification, availability of verification IP, integration with software debuggers, and assertion-based acceleration. It also offers full support of Linux platforms as well as broad support of design languages and standards.

A basic configuration (including nine Incisive simulation licenses that are swappable between simulation and emulation runtime) with a 3.8-Mgate capacity costs about $380,000.

Cadence Design Systems

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