Design Rule Checker Identifies Bugs Early And Assists Design Reuse
The VN-Check design rule checker boosts confidence in the quality of Verilog and VHDL IC designs early in the chip-development cycle. It also helps identify design bugs as early as possible while facilitating the reuse of existing designs. According to its manufacturer, this checker gives designers unprecedented control and flexibility in customizing and organizing built-in rules and in developing their own rules.
VN-Check is part of the Verification Navigator design verification environment, which provides code coverage, test suite optimization, state machine coverage, and circuit activity analysis. The checker uses Verification Navigator's GUI, letting designers quickly navigate through large amounts of data. Also, it provides batch-mode textual reports to simplify integration into back-end flows.
The VN-Check's list price starts at $15,000 for a single language when bundled with the Verification Navigator base configuration. It also lists at $20,000 as a standalone product. The VN-Check CRG costs $45,000.
TransEDA, 985 University Dr., Los Gatos, CA 95032; (408) 907 2000; fax (408) 907 2085; www.transeda.com.
Chip-Level Design System Targets Multimillion-Gate Implementation
The Hierarchical First Encounter (HFE) design system supports chip-level implementation of multimillion-gate, high-performance system-on-a-chip (SoC) designs created through deep-submicron technology. Designers can use it to optimize and assemble the largest next-generation SoC designs. It's based on technology that delivers block-based design-tool capacity while maintaining the ability to optimize traditional flat methodologies.
Its In-Context architecture provides speedy access to the most accurate physical information at all times during the design development. The system also employs the Fast-Track database. This super-lightweight infrastructure delivers the highest capacity and minimum memory and disk requirements. Overall, the HFE is scalable to design sizes up to 100 million gates and more. Furthermore, it reads-in Verilog netlists and LEF/DEF format files.
Available in the third quarter, a 12-month HFE license starts at $105,000. The 12-month license for the SoC First Encounter package, which includes HFE, starts at $245,000.
Silicon Perspective Corp., 3211 Scott Blvd., Ste. 100, Santa Clara, CA 95054-3009; (408) 327-0900; fax (408) 727-4450; www.SIPerspective.com.
Synthesis Tool Suite Manages Multimillion-Gate SoCs
The Volare technology platform adds electronic system level design techniques and global system-on-a-chip (SoC) synthesis capability to current RTL methodologies. This comprehensive, fully integrated front-end solution supports multiple design methodologies, such as architectural, RTL, data path, and gate-level design. The platform also can be used in IP creation, reuse, and exchange.
Its multilevel synthesis technology combines system and logic design for more integration with fewer manual steps, more abstraction, easier flow, and better performance. This technology also reduces design descriptions and enables timing convergence. The platform's Tight feature models the entire gate-level critical path before creating an RTL implementation. Also, the Topomo topology modeling capability addresses front-end timing convergence.
The Architectural Synthesis and Mega Logic Synthesis Modules are now available. Topomo and a full release of the user interface will be available later this year. Contact the company for pricing information.
Get2Chip.com, 2107 N. First St., Ste. 350, San Jose, CA 95131; (408) 452-1094; fax (408) 452-1980; www.get2chip.com.
Timing Sign-Off Tool Extends Static Timing Analysis
The SiliconSmart Timing Sign-Off (TSO) tool lets users selectively refine timing and obtain silicon-accurate timing results directly from popular static timing tools. Its Selective Model Accuracy Refinement Technology (SMART) produces transistor-level accurate results required for timing sign-off. Tightly bound to Envisia Ambit tools through an OLA-compliant API, it builds path models for the entire design.
By using its dynamic instance specific operating point (ISOP) models and SMART capabilities, the SiliconSmart TSO produces accurate models. ISOP models remove 15% to 25% of the pessimism in cell transition delay typically found in static models. Designers, then, can perform in situ critical path analysis, including the timing impact of on-chip voltage variations (IR drops) and significant temperature gradients.
The SiliconSmart TSO's general release is scheduled for the third quarter. It's immediately available for Unix-based workstations from Sun Microsystems. Contact the company for information on term-based licensing for single user and site configurations.
Silicon Metrics, 12710 Research Blvd., Ste. 300, Austin, TX 78759-5321; (888) 828-3736; fax (512) 651-1520; Internet: www.siliconmetrics.com.