Electronic Design UPDATE: September 1, 2004

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Electronic Design UPDATE e-Newsletter
Electronic Design Magazine 
PlanetEE ==> www.planetee.com
September 1, 2004
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Today's Table Of Contents:
1. Editor's View
  * Wanted! Transaction-Level Modeling Standards
2. Focus On ASICs
  * IP Acquisitions Broaden Product Offerings
3. News From The Editors
  * Technique Improves DC Convergence For Spice Simulation
  * PXI-Based Instruments Boost Sample Rates, Memories
  * Public Safety Agencies Seek Software-Defined Radios 
4. Upcoming Industry Events
  * SensorsGOV Expo & Conference
  * Embedded Systems Conference
  * Assembly Technology Expo
  * PCB East
5. Magazine Highlights: August 23, 2004
  * Cover Feature: Engineering Feature -- Chips In Space: On-The-Fly 
Intelligence
  * Technology Report -- Divide And Conquer: On-Chip Hardware Adjuncts 
Accelerate MCUs
  * Leapfrog: First Look -- Low-Level Measurement Gets High-Level 
Treatement
  * Leapfrog: First Look -- Thrifty ICs Tame Multichannel-Audio I/O
  * Design View / Design Solution -- Control High-Frequency Effects When 
Distributing Power To DSPs

Electronic Design UPDATE edited by John Novellino, Executive Editor

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1. Editor's View -- Exclusive to Electronic Design UPDATE
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Wanted! Transaction-Level Modeling Standards

By David Maliniak, Electronic Design Automation Editor

With system-on-a-chip (SoC) designers' interest in architectural design 
exploration rising, it finally seems to be the year of electronic 
system-level (ESL) design methodologies. It's been decades now since 
design complexity forced the move upward in abstraction from gate level 
to register-transfer level (RTL), and the time is well nigh for a move 
to the next level of abstraction, which would be the algorithmic level.
   Proponents of ESL are quick to point to the benefits of 
transaction-level modeling. In particular, emerging SystemC-based 
design methodologies facilitate rich mixed-abstraction modeling 
capabilities. Such methodologies enable designers to begin with 
algorithmic models for their IP blocks, with which they can play 
games with hardware and software partitioning. Then, as they work 
their way toward RTL versions of those blocks, they can simulate in 
mixed-mode, mixed-language fashion, gradually replacing 
transaction-level models with fleshed-out RTL versions until their 
entire system is RTL-ready. Thus these methodologies, as exemplified 
by the Cadence-CoWare partnership, serve to provide a path to 
implementation.
   The sticky part lies in the fact that as of now, there are no hard 
and fast industry standards as to what constitutes a 
transaction-level model (TLM). TLMs come in many shapes, sizes, and 
flavors. These range from the pure algorithmic level, at which there 
is absolutely no distinction between hardware and software, to what 
some term "hardware views," or models that infer hardware-level 
timing and other information that at least imply a direction for 
implementation. In between are various shades of grey, all of which 
represent degrees of abstraction lying somewhere between algorithmic 
and RTL.
   Until standards are defined for TLMs, it'll be difficult for the 
industry to coalesce around an ESL methodology that's portable 
between EDA vendors' tool flows and IP companies' models. We're at a 
juncture at which large IP vendors such as ARM and Synopsys are 
beginning to get on board with providing SystemC models of IP. It 
would be of great help to SoC designers looking to implement ESL 
flows if they could all agree on how to provide those models.
   The Open SystemC Initiative's (OSCI's) Transaction-Level Modeling 
Working Group is in the midst of its efforts to define TLMs. If it 
can't define the models, it at least can define the terminology 
surrounding them, and that's where it has started. "One of the 
problems we have with transaction-level models is the very name 
itself," says ARM's Mark Burton, chair of OSCI's TLM Working Group. 
"Some people are assuming that it is one thing, 'transaction-level 
modeling,' and what has materialized through the Working Group is 
it's actually a number of different styles of models being used at 
different abstraction levels."
   Additionally, says Burton, the concept of TLMs can seem like a 
modeling panacea if not understood in all its nuances. "But as soon 
as you start digging, you discover that it isn't that simple and that 
you need to make a lot of other decisions," says Burton. "Some 
aspects of TLMs aren't yet stable, and others are. And that tends to 
worry people away from it. Which I think, in a lot of ways, is 
unnecessary, because 90% of people are indeed covered now."
   The good news is that OSCI and the Open Core Protocol International 
Partnership (OCP-IP) have collaborated on an interoperable modeling 
structure for TLMs based on SystemC. Burton's TLM Working Group's set 
of definitions and taxonomy for TLMs are a start in the right 
direction. A set of application programming interfaces (APIs) will 
follow, including a transport API that OCP-IP will use for models of 
Open Core Protocol communication channels. Together, these 
developments point toward development of a SystemC-based modeling 
infrastructure that will allow designers to truly leverage the 
concept of transaction-level modeling and form the foundation of ESL 
design flows with a true path to implementation.

To comment on this Editor's View, go to Reader Comments at the foot of 
the Web page:  

Electronic Design UPDATE ==> 
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvg0AC

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2. Focus On ASICs
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***IP Acquisitions Broaden Product Offerings
Two major product acquisitions, one by Mentor Graphics Corp. and the 
other by ARM Inc., will expand the ability of both companies to provide 
system solutions. The acquisition of the Serial ATA intellectual 
property developed by Palmchip Corp. adds to Mentor's large portfolio of 
standards-certified cores and increases the company's IP offerings for 
the growing storage systems market. In contrast, ARM expanded its IP 
capabilities well beyond its family of CPU cores with the acquisition of 
Artisan Components Inc., a leading provider of physical IP components 
for the design and manufacture of complex system-on-a-chip ICs. The IP 
portfolio includes standard cell libraries, embedded memories, 
input/output cells, analog functions, and high-speed interface blocks. 
ARM can now offer more of a system solution to potential customers, 
rather than forcing them to seek another IP supplier to support the ARM 
CPU cores.
     Mentor Graphics Corp. ==> 
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvh0AD 
     ARM Inc. ==> http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvi0AE 

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3. News -- From The Editors
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***Technique Improves DC Convergence For Spice Simulation 
It's long been difficult to achieve dc convergence in Spice simulators 
for analog feedback circuits in which high-gain amplifiers are cascaded 
with active regions that are offset. Today's Spice convergence 
algorithms tend to oscillate and find a solution only by chance. The 
problem stems from the chaotic nature of Spice's numerical iteration 
process. In the real world, such circuits don't oscillate in the time 
domain because capacitors are used to dampen the oscillation. A new 
convergence stepping algorithm implemented by Larry Meares, president of 
Intusoft, has been demonstrated using a coupled two-stage feedback-loop 
circuit employing high-gain amplifiers. With the new ICStep algorithm, 
the circuit converged in only six iterations. Attempts to achieve 
convergence without the algorithm failed after 445 iterations. ICStep is 
the latest enhancement to IsSpice4, a fourth-generation version of 
Berkeley Spice 3F5- and XSpice-based technology.
     Intusoft ==> http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BEtV0Al 

***PXI-Based Instruments Boost Sample Rates, Memories
The PXI-5124 12-bit, dual-channel digitizer and PXI-5422 16-bit 
arbitrary waveform generator double the sample rate and memory depth of 
National Instruments' digitizer and arb product families, raising the 
bar to 200 Msamples/s and 512 Mbytes/channel. The PXI-5124 offers 75-dBc 
spurious-free dynamic range and 150-MHz bandwidth. The PXI-5422 delivers 
less than 6% pulse aberration and a 1.8-ns rise time. The devices, part 
of the company's modular instrument line, use the Synchronous and Memory 
Core architecture. The architecture allows tight synchronization between 
instruments, with a module-to-module jitter of less than 20 ps. Both new 
modules can import external sample clocks, reference clocks, and 
triggers through front-panel connectors or the PXI trigger bus. 
Designers can use the modular instruments to quickly build 
stimulus/response test systems with minimal programming using the new 
SignalExpress interactive measurement software as well as LabView 7.1 
and NI TestStand test management software. The PXI-5124 digitizer and 
the PXI 5422 AWG each start at $5995.
     National Instruments ==> http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvj0AF 

***Public Safety Agencies Seek Software-Defined Radios
A strong majority of public safety workers, 88%, believe that 
software-defined radios (SDRs) could help solve the many 
interoperability problems of communications between departments, 
according to a study by Venture Development Corp. Because they use 
radios operating on different frequencies and with different protocols, 
public safety personnel often resort to swapping radios or sending 
communications gateways to incident sites. Both cause delays and 
confusion in critical situations, says VDC. Similar issues caused the 
Department of Defense to establish the Joint Tactical Radio System 
program, and plans call for spending an estimated $4.7 billion on SDR 
devices over the next four years. But because of problems like high cost 
and lack of a civilian standard for SDRs, no commercial products exist, 
says the Natick, Mass.-based market research firm. "It will probably be 
several years before SDRs penetrate the public safety community," says 
Chad Hart, VDC's datacom and telecom practice director. "However, 
successful military implementations and demand from public safety 
agencies will promote product development."
     Venture Development Corp. ==> 
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvk0AG 

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4. Upcoming Industry Events
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Sep. 13-15, SensorsGOV Expo & Conference
Virginia Beach, Va.
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKch0As

Sep. 13-16, Embedded Systems Conference
Boston, Mass.
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BGCX0A1

Sep. 28-30, Assembly Technology Expo
Chicago, Ill.
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvl0AH 

Oct. 4-8, PCB East
Manchester, N.H.
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvm0AI 

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5. Magazine Highlights
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In case you missed them, here are some of the high points of our most 
recent issue.

August 23, 2004:

* Cover Feature: Engineering Feature -- Chips In Space: On-The-Fly 
Intelligence
Joint effort to develop rad-hard SOI chips synergizes commercial and 
military worlds to produce a network of security satellites that share 
and process data on the spot in orbit.
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvn0AJ

* Technology Report -- Divide And Conquer: On-Chip Hardware Adjuncts 
Accelerate MCUs
Enhanced on-chip peripherals or asymmetric multiprocessing helps 
optimize performance and power consumption, avoiding the need to resort 
to higher-power processors.
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvo0AK

* Leapfrog: First Look -- Low-Level Measurement Gets High-Level 
Treatement
A series of codecs and class-D drivers provides a gaggle of inputs and 
outputs for car and home audio systems without resorting to fistfuls of 
ADCs and DSPs.
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvp0AL

* Leapfrog: First Look -- Thrifty ICs Tame Multichannel-Audio I/O
Able to perform 266 million searches/s, the Ayama 20000 NSE uses dual 
LA-1 ports to divvy up the tasks between two NPUs for faster throughput.
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvq0AM

* Design View / Design Solution -- Control High-Frequency Effects When 
Distributing Power To DSPs
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvr0AN

For the complete Table of Contents, go to 
Electronic Design ==> 
http://lists.planetee.com/cgi-bin3/DM/y/eA0Gl4E70Fh10BKvs0AO

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CONTACTS: Electronic Design UPDATE e-NEWSLETTER
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mailto:[email protected]

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