Physical IC design flows are studded with analysis tools for numerous parameters, including leakage power, IR drop, electromigration, and timing. Now, Gradient Design Automation seeks to add thermal analysis to the mix in the form of its FireBolt analysis engine, which creates a 3D full-chip temperature map to account for the electrical effects of thermal gradients across a semiconductor die.
Today's design flows typically use a constant-temperature methodology, attempting to account for temperature variations by considering a large number of statistical temperature points. Each of these temperature data points assumes a constant on-chip temperature, which is rarely a valid assumption at 90 nm. Not only that, the statistical distribution is generally aimed at worst-case situations, which inhibits design optimization due to the large design margins needed in such situations.
The engine locates maximum temperature differences on the die due to device and wire self-heating. It provides a list of devices and their locations based on temperature as well as a list of metal and interconnect temperatures. Contour maps show temperature gradients to aid in hot-spot removal.
Gradient's FireBolt engine, which has already been integrated into Cadence's Encounter flow, comes into play at various levels of abstraction during physical design (see the figure). Floorplanning tools will use temperature-analysis results to place blocks for optimal thermal gradients.
The power-rail and clock signals are analyzed for IR drop, electromigration, and delays. In place and route, the thermal-analysis function will query cell moves that minimize the temperature gradients within the chip.
The FireBolt thermal-analysis engine is available now under time-based licensing. Pricing starts at $150,000.
Gradient Design Automation