Enhanced RTL Debugger Tacks On Device Support

Aug. 4, 2003

With the Identify RTL debugging tool, FPGA prototyping designers can functionally debug their hardware directly in the RTL source code. Version 1.2 of Identify supports Xilinx Virtex-II Pro FPGAs, Actel ProASIC and ProASIC Plus FPGAs, and Agilent's traceport cable. Using Identify, designers can add triggers to either the data or control paths in their RTL code and specify signals to be watched. The tool supports Verilog and VHDL, as well as mixed-signal designs. One-year time-based licenses start at $15,000.

Synplicity Inc.www.synplicity.com

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.