With the Identify RTL debugging tool, FPGA prototyping designers can functionally debug their hardware directly in the RTL source code. Version 1.2 of Identify supports Xilinx Virtex-II Pro FPGAs, Actel ProASIC and ProASIC Plus FPGAs, and Agilent's traceport cable. Using Identify, designers can add triggers to either the data or control paths in their RTL code and specify signals to be watched. The tool supports Verilog and VHDL, as well as mixed-signal designs. One-year time-based licenses start at $15,000.