Electronic Design

Enter The Age Of Design For Manufacturability.

The broad adoption of virtual prototyping and physical synthesis tools have helped reduce the number of synthesis/place-and-route iterations. They also helped RTL coders avoid what they've long dreaded—having to become physical-design experts.

But these tools only work as well as the underlying assumption that drawn layouts equal on-silicon circuitry. Each new sub-100-nm process generation increasingly renders this assumption invalid. Because silicon feature sizes are now smaller than the wavelength of the light used to create them, other techniques are now required to ensure the design's fidelity in the physical realm (see the figure).

Here, technologies such as resolution enhancement technology (RET), which became mandatory starting at 180 nm, step into the fray. At 180 nm, RET served primarily for yield enhancement. At 130 nm, RET facilitated yield creation. But at 90 nm, there simply is no yield without RET. With imaging equipment featuring wavelengths below 193 nm still in the wings, RET will have to continue to do the job at subnanometer geometries.

Concerns such as signal integrity and power issues, post-layout applications, and resistive and other speed-related defects, all formerly relegated to a background noise level, took center stage at 130 nm. These issues, which significantly affect chip yield (and failure), form the foundation for a new world of design for manufacturing (DFM). If we're to have a viable semiconductor industry for the 90- and 65-nm nodes, the EDA industry must enable designers to consider and optimize for manufacturing at each stage of the design, verification, tapeout, and test process.

Ultimately, this will require a new generation of DFM tools that aren't merely post-layout reactions to crises that arise from analysis of the physical design. Three critical components are needed to make a DFM tool truly productive:

  • An accurate and current understanding of the process-design interactions in the fab and how they affect yield;
  • A characterized model that reduces such information into a numerical representation for use by EDA design tools to make millions of correct DFM decisions;
  • Insertion of this information early into the design flow so these tools can make those millions of correct DFM decisions—and do so without hurting the accuracy, timing, or power calculations.
  • Accurate on-silicon circuit performance to feed back to logic design/prototyping tools and identifying and repairing physical-design problems before committing to tapeouts are both critical to the design process. So, next-generation physical design tools must be manufacturing-aware, namely, back-annotate precise (i.e., not virtual) manufacturing distortions for use in optimizing the design while remaining transparent to physical designers.

    Together with virtual silicon prototyping tools, this ensures quicker and more reliable design-to-manufacturing closure. And, ultimately, there's less of a need for physical designers to become experts in manufacturing enhancements.

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