Electronic Design

Enterprise-Level Verification Bonds Specialists And Languages

With the announcement of the Incisive Enterprise family of verification products, Cadence rolls out an enterprise-level suite that knits together various types of verification specialists and languages. The family, which is the top tier in Cadence's Incisive functional verification platform, is aimed at multi-specialist SoC project teams. It automates and coordinates the verification process across the block, chip, and system levels.

Integrating verification process automation technology from Cadence's acquisition of Verisity, the new offerings span system modeling, HDL and assertion languages, high-end formal and dynamic engines, verification IP, and analysis capabilities tailored for the various specialists that touch the verification process.

The family includes the Incisive Specman simulator, which provides direct-kernel integration of the Incisive simulator with block- to system-level testbench automation from Verisity's Specman Elite. The suite implements a mixed SystemC and e verification-language transaction-level methodology that links systems and verification specialists.

A key element of the family is the Incisive Palladium hardware-assisted verification platform. The hardware platform brings to the table high-speed acceleration, hardware/software coverification, and system-level and post-silicon verification capabilities.

The Incisive Enterprise products come closely on the heels of the Incisive Design Team family, a suite of products and methodologies that bring the same level of cohesiveness to the RTL design-team level.

E Language Standardization
In related news, Cadence announced that the IEEE sponsor ballot for P1647 e standardization has passed overwhelmingly. The ballot by the sponsors of the proposed standard closed on Oct. 27. Editorial comments will now be addressed and the ballot will be recirculated for final approval before it is submitted for ratification on March 28, 2006.

Cadence Design Systems

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