Electronic Design

Equivalence Checker Formally Verifies Bug-Free RTL Clock Gating

Clock-gating techniques for power management are coming into greater favor among RTL designers. Often, designers will instantiate clock gating as a means of conserving power by turning off the clocks to quiescent sections of the system.

Unfortunately, these techniques typically are employed late in the RTL-design game, so it's difficult to determine their effectiveness. Even more critical to ascertain is whether the instantiation of clock gating has introduced functional bugs into the system. Clock gating has proved to be difficult to verify in a test-bench-driven verification flow. In such flows, it's difficult to control and observe.

Into the breach comes Calypto Design Systems and its SLEC CG (Sequential Logic Equivalence Checking for Clock Gating). SLEC CG builds upon Calypto's existing SLEC family of RTL equivalence checkers by adding the ability to functionally verify RTL power optimizations without the need to write specific test-benches or run simulations.

SLEC CG quickly identifies bugs that have been introduced through the instantiation of RTL clock gating. The tool formally verifies the changes made to the RTL, finding elusive corner-case bugs and giving designers an efficient block-level debug environment.

Additionally, the tool automatically detects clock-gating logic and ensures that the enabling logic is stable in relation to the clock edges. It verifies all possible input sequences that enable and disable clocks. It also checks complex clock-gating schemes that cross hierarchical and block boundaries. These conditions can be very difficult to control and observe using test-bench-driven verification techniques.

The clock-gating verification capabilities nicely complement Calypto's SLEC RTL and System packages. SLEC RTL compares an RTL design specification against a "golden" reference design. SLEC RTL detects design differences and automatically generates counterexamples for debug. SLEC System proves functional equivalence or locates differences between SystemC/C++ models and RTL.

SLEC CG is available immediately with support for VHDL and Verilog. Design teams with existing licenses will receive SLEC CG as part of their SLEC RTL and SLEC System suites. The tool runs under Linux and is priced from $125,000.

Calypto Design Systems
www.calypto.com

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