Design at the electronic system level (ESL) continues to gain traction, as system-level modeling has moved past the system architect into the realm of software and hardware designers. As a result, ESL design is becoming a mainstream reality.
The mainstream adoption of ESL is not just sheer optimism. Power-efficient, software-rich consumer devices such as PDAs, cell phones, and video imaging are driving adoption. A confluence of three formerly disparate design challenges — and the availability of practical, commercial tools to address them — is mandating adoption. These challenges, in no particular order, are: power management, hardware/software co-design, and the intractable problem of verification. ESL raises the abstraction level of design to address complexity. ESL, which is defined here as all design above the register transfer level (RTL), has become the entry point for hardware design.
With RTL design it is becoming more difficult to achieve low-power circuits while still meeting performance, area, and manufacturability requirements. Modification of RTL after it's been functionally verified is extremely time-consuming and generally discouraged. More so, few designers have the time to explore multiple RTL micro-architectures. Examination of power architectures at ESL, on the other hand, affords a greater opportunity to save power. There, through performance of sequential transformations, designers of power architectures can make quick tradeoffs and arrive at an optimal design.
Given today's requirements, hardware and software design — or hardware/software co-design — must be simultaneous and coupled. In older generations of design, hardware could be done first and software could be integrated later. This is no longer valid due to the large amount of legacy software, detailed programming interfaces, and time required to develop software applications. ESL solves these problems by providing one model of both software and hardware that runs fast enough to validate hardware algorithms and verify software.
It is common for teams to describe the entire hardware architecture at the system level to confirm functionality and performance. In doing so, ESL design ensures that power and timing can be analyzed early, when changes are easier to make and greater improvement can be achieved. In advanced ESL flows, this "prototyping effort" is reused as the cornerstone of RTL verification. By using the prototype as an "executable specification" or "golden model," designers ensure their hardware works exactly the same as they verified it would in the prototype system.
Going forward, the challenge for the semiconductor industry is to keep up with the broad requirements of today's markets while coping with the physical realities of smaller technologies. Correspondingly, the demand on EDA vendors is to provide complete ESL solutions that fit into today's existing RTL flows and solve the challenges of power, hardware/software co-design, and verification. Successful ESL adoption raises the productivity of designers while not requiring a retooling of existing methodologies. Simply put, RTL alone is not sufficient and ESL must coexist with RTL.
The last couple of years provide evidence that designers are embracing ESL. Among other factors, the acceptance of C-based modeling languages, creation of system modeling environments, adoption of high-level synthesis tools, and emphasis on hardware/software co-verification all point to this adoption. Many of these current ESL tools fit nicely into an RTL flow. It is now possible to model an entire system, including RTL and system-level intellectual property (IP) models in an ESL design flow. New verification tools can prove that hand-generated hardware models or those generated by system synthesis are functionally the same system-level models. And that is just the beginning.
Make no mistake: ESL is becoming the entry point for design. ESL power, hardware/software, and verification tools have made their way into mainstream design flows. Indeed, it's an exciting time as designers embrace ESL solutions.