Electronic Design

ESL Tools Analyze, Optimize CPU-Based Designs

Automating the process of optimizing and accelerating processor-based designs, the Triton tool suite from Poseidon Design Systems is based on a SystemC software and hardware co-simulation environment. Furthermore, the suite employs transaction-level modeling (TLM) and Poseidon's hardware/software partitioning technology to co-simulate hardware and software at the architectural level. After that, it tunes the embedded system for optimal performance, power, and cost.

Triton Tuner is a simulation and analysis environment based on SystemC. It analyzes embedded-system performance, including software (using performance counters, code profiling, and bottleneck analysis) and hardware (checking memory bandwidth, pipeline stalls, and cache misses). It helps designers fine-tune their system architecture by determining the optimal hardware/software partition for a given application and by generating more efficient code based on the new partition.

Triton Builder is a synthesis tool that automatically generates algorithm-specific hardware acceleration blocks in RTL. These blocks offload the math-intensive algorithms from the host processor as determined by Tuner's partitioning results.

In a benchmarking effort, Poseidon has implemented a wavelet encoder for a JPEG 2000 application. This yielded a 23× reduction in execution cycles from 81.13 million cycles to 3.54 million cycles.

Triton Tuner and Builder are available now, both separately and as a suite. Triton Tuner ranges from $30,000 to $50,000 for a one-year, time-based individual license. Triton Builder ranges from $70,000 to $95,000. The suite ranges from $95,000 to $140,000.

Poseidon Design Systems
www.poseidon-systems.com
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