Despite being touted early on as a higher-level alternative to HDLs, hardware modeling in SystemC has suffered for its lack of a path to implementable RTL. Further, SystemC does a poor job of expressing concurrency.
Bluespec, which first came to market with extensions to SystemVerilog and tools for ESL synthesis, has turned its attention to the SystemC language and its applicability to hardware architecture and design. With its ESL Synthesis Extensions (ESE) for SystemC, Bluespec hopes to create a unified environment for modeling, design, verification that raises design abstraction to a level above RTL.
Synthesis from SystemC into RTL has, until now, been limited to purely algorithmic functions. But with the addition of ESE, SystemC elevates the description and synthesis of control logic and complex datapaths for SystemC-based designers.
The language gains modeling accuracy with full hardware architecture and implementation support (see the figure).
The extensions add two key enhancements in the areas of concurrency and communications: atomic transactions, or rules; and automated, formal interface contracts, or interface methods. In addition to the language reference manual, other documentation, and code examples, these extensions are freely downloadable and work with the standard Open SystemC Initiative (OSCI) reference simulator, for untimed simulation, and with the GNU Compiler Collection (GCC) compiler.
The basic ESE implementation is freely available from Bluespec's Web site. This version supports the ESL-synthesis language extensions for untimed simulation with the OSCI simulator. ESEPro is Bluespec's premium implementation, which adds support for clock-scheduled simulations. Bluespec also has contacted OSCI about donating the ESE technology for a future update of the SystemC standard.
ESEPro pricing starts at $35,000 for a one-year time-based license. ESEComp, which synthesizes ESE SystemC designs into Verilog RTL, will be released later this year. Demonstrations are scheduled for July's Design Automation Conference.