In case you haven't noticed, an interesting trend is in the offing, and it all centers on one thing—programmable logic devices (PLDs) such as field-programmable gate arrays (FPGAs). In recent years, they've carved out a niche in the prototyping arena. They let designers get prototypes up and running in a few weeks, while an ASIC takes a few months. This process has become so popular, in fact, prototyping with an FPGA and moving to an ASIC for volume production has become a common procedure.
The ability to quickly deploy FPGAs isn't the only advantage traditional ASIC designers are eying. Consider for a moment that the programmable market is one of the fastest growing segments of the semiconductor industry today. Device density is unmistakably a large contributor to this growth.
"Xilinx has recently announced a new member of the Virtex family supporting up to two million gates," says Herman Beke, CEO of Frontier Design. "This is just the start of an unstoppable trend toward higher device density. We can expect the number of gates available on an FPGA to double every year for the next few years."
These high densities, coupled with new, inexpensive, high-quantity programmable devices, mean that FPGAs no longer are seen as just an alternative to the ASIC prototype. On the contrary, with benefits like faster time-to-market and the ability to handle changing design requirements, FPGAs are now themselves being used for volume production. For many designers, the line between ASICs and FPGAs has blurred (see "Look For The Signs," p. 74).
EDA vendors have stood up and taken notice of this upsurge in the use of FPGAs and similar devices. These companies are coming to the market with a host of new tools and enhanced design features to make it easier for the traditional ASIC designer to migrate to FPGAs. Additionally, tool vendors and device suppliers are forming alliances to promote designs based on programmable logic. This translates into more options for the designer. The only questions involve how designers will choose between FPGAs and ASICs, which tradeoffs will be associated with that decision, and what obstacles lay ahead for the programmable design space.
What's the big deal about programmable logic, you ask? After all, it's been around for a long time. Why should ASIC designers, or any other types of designers for that matter, want to use it now (see "The FPGA Migration Is On," p. 78)? It's a fair question that's relatively easy to answer.
Engineers are opting to use FPGAs rather than ASICs because they're flexible, quick to deploy, and much more affordable than they were in the past. Did you realize that in today's consumer-driven marketplace, the lifetime of a product is often shorter than its development cycle? Time-to-market pressures are even more stringent now than in the last few years. Dealing with this pressure means designers need greater design flexibility.
The flexibility in FPGAs stems from their inherent reprogrammable nature. As Phil Lewer, product marketing manager of Viewlogic, explains, "This allows additional functionality to be added to an end product that is actually deployed in the field without having to physically modify the board. In contrast, if you want to change the functionality of an ASIC, you would need to make a new ASIC, resulting in physical changes having to be made to the board."
Along with this flexibility comes a lower risk factor that many designers find desirable. With FPGAs, mistakes can be corrected and design revisions can be made simply by reprogramming them. By comparison, if the design is realized in an ASIC, any mistake will require a new set of masks and a new production run. This is a cost and time drain.
Such benefits have become increasingly advantageous for engineers designing consumer-based end products containing one or more standards. Take high-definition television (HDTV) consumer products. The standards governing the mechanism by which they deliver high-definition picture quality are in flux. In this case, the use of programmable technology would effectively enable the product configuration to be reprogrammed in the field, should the standard change after the set has been built and shipped to a customer.
It's not all that surprising, then, why ASIC designers might opt to use an FPGA instead of an ASIC for everything from prototyping to low-volume system production uses like beta testing and volume production. Nor is it any surprise that programmable logic tends to naturally lend itself to use in certain applications areas. It is, for instance, ideally suited for those applications where time-to-market is far more important than absolute performance or product cost, or where system performance is dictated by an interface speed. This is the case with networking and telecommunications applications.
Some designers might be surprised that this programmable-logic trend isn't limited to the traditional ASIC design community. Bill Wignall, president and chief operating officer of Electronics Workbench, points out that "PLDs/CPLDs (complex programmable-logic devices) are now sufficiently complex to handle pc boards. As a result, we now see designers putting what used to be on a board onto PLDs/CPLDs."
If, by chance, you happen to be one of the designers migrating to FPGA/PLD designs based on hardware description languages (HDLs), you might be curious to know if design tools are available in this space—and if so, where to find them. Depending on your level of design expertise and what you plan to design, your first option may be to go to the device suppliers. Oftentimes, they have tools ready and available for you to use. Best of all, they're usually free.
On the other hand, if your design requirements demand a higher level of tool functionality or performance, you should turn to the nearest EDA tool vendor. Many of them now offer not only a host of best-in-class tools, but a programmable technology-based design flow and methodology as well.
Some of the vendors working in this design space include Mentor Graphics with its Exemplar Logic and Model Technology subsidiaries, Cadence Design Systems, Synopsys, Viewlogic Systems, Synplicity, and the Hyperlynx Division of PADS Software—just to name a few (Fig. 1). Hoping to provide an easy-to-use design flow for the designer, many of these companies are actively involved in ongoing partnerships and development agreements with suppliers such as Actel, Altera, and Xilinx.
If you're one of the designers using or wanting to use programmable technology, you can consider yourself lucky. Programmable-technology suppliers and EDA vendors desperately want your business, and they're not averse to working hard to gain it. If you want to use their tools and technology to conduct early design prototyping, fine. If you want to initiate volume production, even better. This means more design starts for the device supplier, which in turn translates into more money. It also means that vendors and suppliers are more than willing to help you in any way they can.
If you're a traditional ASIC designer, making the migration to FPGA/PLD-based design isn't that difficult a stretch. You are, after all, well versed in the art of design using the VHDL/Verilog HDLs. As a sophisticated designer, you understand the nuances of creating very complex designs with high gate counts.
While these skills will serve you well when designing with programmable logic, you still have to learn some tricks of the trade if you want to get the most speed and performance out of your FPGA/PLD-based design. Often, the only way to learn these trade secrets is from vendors and suppliers. Luckily, these vendors so desperately want your business, they'll gladly share this information with you. They're willing to educate you, train you, and even hold your hand through the entire design process, if that's what it takes to make you, and in turn them, successful. Best of all, many will do this free of charge.
This is good news, especially if you're migrating up the FPGA/PLD food chain. These designers are used to designing with programmable logic, but they've done so using pushbutton design tools based on schematic capture—not based on HDLs. This methodology works well with smaller gate counts, say in the 5k to 10k range. But it breaks down when you begin to talk about gate counts on the order of 100k or 1000k.
Unfortunately, there isn't a manual that adequately explains how to make this transition or how to completely leverage the power and benefits of FPGAs/PLDs. Again, this is where the current generosity of suppliers and vendors will play an increasingly important role. They can help you through this transition, answer your questions, and show you what you need to know to get your job done.
Despite the benefits from the recent dramatic increases in density, programmable logic isn't without its limitations. ASIC designers who have been pushing the performance of their designs will find that FPGAs don't offer the same level of performance. Additionally, today's FPGAs have finite numbers of clocks. Handling sequential logic is difficult if not impossible, and latches do not exist.
"Although the speeds and densities of FPGAs/CPLDs have improved tremendously, they require additional logic to make them programmable," explains Jackie Patterson, director of marketing at Synopsys. "This means that they are not as fast and as dense as leading-edge standard cell technology."
Vince Hopkin, director of translation ASICs at American Microsystems Inc., says that "Due to cost and some logic issues, neither the FPGA nor the PLD can always replace the use of an ASIC once you reach the production stage. For that reason, designers who use FPGAs and PLDs need to keep in mind the eventual transition that will be required for volume manufacturing of the device they are working on. By designing with future translation in mind, the designer simplifies the conversion and holds down costs for his or her company."
There are a few other key tradeoffs you might want to consider before taking the plunge into the realm of FPGA/PLD-based designs.
First, be aware of your architecture. Programmable logic is often characterized by highly specialized architectures. As such, your design will be constrained by the architecture of the programmable logic you are using. You must obey the rules set forth by that particular PLD. Also, be sure to use a synthesis tool that isn't just cognizant of your device's architecture, but also sensitive to its nuances.
Second, check the design-flow compatibility with ASICs. If you're going to go back and forth between PLD and ASIC tools, chances are you'll want to reuse code and scripts between them. If this is the case, make sure your two tool sets are compatible with each other.
This design-flow compatibility is especially critical when you want to combine programmable logic and ASICs in a single design, such as for a system-on-a-chip (SoC). "If you need a microcontroller or an analog-to-digital or digital-to-analog converter in your system, for instance, then you cannot put that functionality in one single FPGA chip. This can be done with an ASIC approach and embedded cores," Beke says. "Many FPGA vendors have already recognized this problem, however, and are now working on hybrid versions of their FPGAs, including blocks such as microcontrollers and RISC cores. Designers can expect this disadvantage to disappear soon."
Also, beware of mapping. "Mapping is a phenomenon that is common to FPGAs and not to ASICs," Lewer notes. "In the ASIC world, what you design is what you get. Gates in equal gates out. However, in FPGAs, Boolean gates get mapped to the physical elements of the FPGA vendor's architecture. As a result, internal signals may be mapped out and test benches that may probe into a design for functional simulation might become useless because the nets that have been probed have been removed in the mapper."
Be sure you choose tools with quality mapping algorithms. Also, you must fully understand how mapping will affect what you can and can't do when designing with FPGAs. In the ASIC design world, the designer hands a netlist over to an ASIC house for placement and routing. In the FPGA design process, though, you will be responsible for the entire flow, including the place-and-route procedure. If you aren't familiar with this process, make sure your tool vendor is willing to provide the support you need to keep the design process rolling, even when you hit a rough spot.
Finally, don't forget about verification. Another limitation to working with FPGAs relates to prototyping. As Patterson explains, "ASIC verification is a huge challenge, and with FPGAs getting so large, they increasingly appear to be a viable way to verify at hardware speeds rather than limiting functional verification to a software simulator. But while the densities of FPGAs are increasing with Moore's Law, the interconnect on the package is not. This leaves the verification team looking for the best way to spread the ASIC functionality across several FPGAs—not to mention the fact that they may have to build special boards to mock up the prototype."
If you fall into this category, Synopsys suggests purchasing a prototyping system like Aptix's model. Or if you want to make your own boards, you might want to get a commercially available, fully automatic partitioner to help you past the interconnect problem.
In addition to carefully weighing the tradeoffs prior to deciding to go the FPGA/PLD route, you also should be aware that technology challenges still lie ahead. Perhaps one of the greatest obstacles that must be overcome by EDA vendors and device suppliers alike is performance. Granted, there are a lot of ways to drive it up, but the key to ultimate success seems to be in finding a way to tightly link synthesis with the place-and-route function.
This link is important because as FPGA/PLD gate counts rise, timing closure becomes a huge problem. In other words, these devices aren't immune to the problems caused by the shrinking design geometries that have traditionally affected IC designers over the past five years. Here, deep-submicron (DSM) design, characterized by geometries of 0.25 µm and below, forces designers to acknowledge and deal with a host of parasitic effects that were previously considered negligible.
At such small geometries, many of the design tools and methods for optimizing a design to meet timing and performance simply cease to work. Wireload models no longer offer an accurate representation of design circuitry. "With programmable-logic devices in the multi-million-gate range and performance requirements well above 100 MHz, it is increasingly difficult for designers to reach timing goals without numerous iterations through synthesis and place and route," says Andy Haines, vice president of marketing at Synplicity.
Meeting timing goals is a crucial issue that designers cannot take lightly. Meeting these goals can translate into significant cost savings for high-volume applications. As timing improves, designers can use a less expensive, lower-speed-grade device. Depending on the number of devices purchased, this savings can amount to tens of thousands—or even hundreds of thousands—of dollars.
On the ASIC side of the world, vendors are dealing with the timing-closure problem by incorporating physical information such as placement and layout into the synthesis run. Now, EDA vendors are attempting to adapt the same sort of approach to deal with timing closure in the FPGA/PLD-design arena. Of course, solving this problem in the FPGA/PLD-design space will need more than tools and technology. It also will require a tight working relationship or partnership between device suppliers and synthesis vendors.
Developing new technology to address this issue is definitely within the realm of possibility for some of the synthesis vendors. Mentor Graphics is currently working on a physical synthesis solution. Expect to see an announcement pertaining to this work later in the year. Synplicity is already ahead of the game, though. It recently debuted its physical-synthesis tool, known as the Amplify Physical Optimizer (Fig. 2). Specifically targeted at programmable-logic designers, it merges physical design characteristics with synthesis to achieve optimum circuit performance.
Essentially, the user assigns physical constraints to the design after HDL source-code compilation but before mapping. A graphical physical-constraints editor operating at the register-transfer level passes physical information to a host of newly devised algorithms. The algorithms then simultaneously employ timing and physical constraints to improve circuit performance. Physical-synthesis techniques such as interconnect-based logic optimization, automatic logic replication, and boundary optimizations on critical paths further improve performance without changing the HDL source code.
Instead of using traditional synthesis and floorplanning to improve design performance, the Amplify tool lets designers use synthesis optimizations to improve circuit performance.
Synplicity says that with an approach like this, designers can expect up to a 40% timing-performance improvement over traditional synthesis alone. With these possible performance gains, it's easy to understand why physical synthesis will play such a key enabling role for the multi-million-gate FPGAs rapidly making their way to the market.
New ASIC starts are declining as FPGAs get larger, faster, and cheaper. Naturally, you might question whether or not the very existence of the ASIC marketplace is in jeopardy. While it's a fair assessment to say that FPGAs are challenging the traditional ASIC business model, it's important to keep in mind that the ASIC business is a moving target. As the threat of FPGAs becomes more pronounced, ASIC vendors will counter by changing the very nature of what ASICs look like and perhaps even how they are used. They simply will have no choice if they are to have any hope of keeping their fabs full.
Speculation as to just how the ASIC business model will adapt centers on the market splitting into two diverse segments. One part will consist of the portion of the prototyping and design market that normally uses ASICs migrating to FPGAs. The other faction, the rest of the ASIC business, will migrate to SoCs. In other words, SoCs will be composed of FPGA-based blocks or cores.
Rosemary Maguire, senior corporate applications engineer at Escalade, agrees with this assessment. "Most designers view programmable technology as another ingredient to a complex SoC," she says. "Future ASIC vendors will incorporate that technology along with their other high-performance IP to deliver a total solution."
Maguire continues: "While FPGAs augment the ASIC design process, they will never replace it. With the expansion of current SoC capabilities, the integration of different pieces of intellectual property is more streamlined, minimizing the penalties associated with complex SoC designs, such as speed-area tradeoffs, power consumption, and crosstalk. What we will see is the use of more FPGAs in complex ASIC designs that are targeted for reuse. Reused ASIC components can be partitioned into separate FPGA components."
For the time being, then, there appears to be more than enough space for the FPGA/PLD and ASIC design spaces to coexist. More often than not, if you need truly reliable, high-volume, leading-edge technology, you will have no choice but to use an ASIC. Increasingly, though, FPGAs will take the lower-gate-count and lower-performance segments.
"The use of FPGAs in their former role of substitutes for small ASICs in low-volume production roles is leading to the replacement of the small ASIC," says Ralph Zak, vice president of marketing at Aptix. "However, the cost of the largest FPGAs does not permit them to replace comparable-complexity ASICs. Furthermore, the complexity of ASICs is increasing as fast as semiconductor technology allows it to increase. Consequently, programmable logic like FPGAs appears to be replacing only the smallest of ASICs, not the larger complex ones, and the 'replacement ASIC target' for the FPGAs is a moving target."
According to Lewer, "ASICs will be relegated to extremely high-density applications. Because of the risk and cost involved in doing such large ASICs, companies will be looking to leverage them. That means that the ASIC will be used as an ASSP (application-specific standard part). Once an ASIC becomes an ASSP, the only way to differentiate the end product that contains the ASIC is through either software or FPGAs."
Ultimately, whether ASICs or programmable-logic devices—like FPGAs—prevail isn't the issue. The crucial point is that designers hampered by stringent cost and time-to-market requirements now have another viable design option. Isn't that what's really important? And if FPGA and ASIC suppliers are forced to revamp their business strategies along the way to present more competitive solutions to the design community, well, that's just icing on the cake!
|Companies Listed In This Report|
American Microsystems Inc.
Cadence Design Systems
Exemplar Logic Inc.
Frontier Design Inc.
PADS Software Inc.
Mentor Graphics Corp.
Model Technology Inc.
Viewlogic Systems Inc.