Debuting as the first member of the company’s third generation big-fast-wide (BFW) PLD family, the ispMACH 5256B is the first of four devices offering logic capacities from 128 to 512 macrocells, speeds up to 3.5 ns, and operating frequencies to 275 MHz. This initial PLD features 2.5V operation, pin-to-pin delays as fast as 4 ns, operating frequencies up to 250 MHz, and advanced I/O standard support, such as GTL+, HSTL, and SSTL. General-purpose interface support includes LVTTL or LVCMOS at 3.3V, 2.5V or 1.8V. Reportedly, its 68-input/32-macrocell logic blocks can accommodate wide logic functions such as those in 32- and 64-bit systems. Future members of the family will include logic densities of 256, 384, and 512 macrocells in a variety of package and I/O options. The ispMACH 5256B is available now in 128-pin TQFP, 208-pin PQFP, and 256-ball fine pitch BGA packages with prices starting from $8 each in high-volume. LATTICE SEMICONDUCTOR CORP., Hillsboro, OR. (503) 268-8000.