Electronic Design

Formal Verification Tools Check SoCs Down To Transistor Level

Targeted for users of next-generation physical design closure tools, customer-owned tooling (COT) flows, and advanced ASIC flows, a new suite of formal verification products reaches into the physical domain for system-on-a-chip (SoC) applications. The Conformal Logic Equivalence Checker (LEC) and Transformal Logic Transistor eXtractor (LTX) perform advanced verification on all logic blocks of complex SoCs, from register-transfer level (RTL) to final layout-versus-schematic netlist comparisons. Together, the tools make up a flow Verplex terms Conformal Layout Versus RTL (LVR). Blocks checked include memory, compiled datapath, memory control, intellectual property cores, complex I/O, and full-custom logic. Traditionally, formal verification tools have not reached the transistor level, missing mistakes made in the layout process and other back-end steps. Shipping now, the tools support 64-bit HP, Sun, and Linux platforms. Conformal LEC is priced from $105,000; Transformal LTX from $95,000; and Conformal LVR (available in the third quarter) from $105,000.

Verplex Systems Inc.
www.verplex.com; (408) 536-0300

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