Through tweaks to existing tools and development of new ones, Mentor Graphics has put together a new release of its front-to-back set of design tools for analog/mixed-signal (AMS) ICs. The flow addresses design entry, simulation, layout, verification, and extraction of AMS system-on-a-chip (SoC) designs.
Included within the flow is Design Architect-IC, a capture and AMS SoC design cockpit; ADVance MS, a single-kernel simulator for analog, digital, transistor-level, and RF simulation; IC Station for physical layout and implementation; Calibre for physical verification; and Calibre xRC, a full-chip, transistor-level parasitic extraction tool.
AMS SoC designs depend on integrated analog blocks such as analog-to-digital and digital-to-analog converters, phase-locked loops, memory subsystems, and RF modules. With simulation now a bottleneck in the design process, ADVance MS lets designers evaluate performance at the chip level before pushing each of these diverse blocks through its own design flow. The simulator includes the Mach TA engine for accurate verification of transistor-level timing at speeds up to 1000 times faster than Spice-based simulators. ADVance MS also includes the Eldo RF engine for fast simulation of the RF blocks in typical transceiver designs (see the figure).
New to the AMS flow is Calibre xRC, which combines the capacity and hierarchical geometry processing of the Calibre engine with the accuracy and layout-versus-schematic (LVS) integration of xCalibre. The tool uses a model-based engine to map the 3D-characterized structure to real net segments for optimum performance. It extracts accurate parasitics, including coupling capacitances, by considering all relevant geometries from substrate through top metal if necessary.
Calibre xRC is currently in beta release with customer shipment scheduled for the third quarter. Pricing starts at $140,000. Call Mentor Graphics for pricing on other tools in the flow.
Mentor Graphics Corp., www.mentor.com; (503) 685-7000.
