Many design teams now strive to create a viable design specification for early hardware/software coverification. Esterel Technologies' latest Esterel Studio release fills that bill by allowing designers to capture a design specification and then automatically generate the hardware description in RTL or C.
The Esterel Studio 5.2 tool suite includes an editor; simulator; assertion-based verification; and VHDL, Verilog, C, and C++ code generators. It's intended for use in design and verification of complex consumer and multimedia systems-on-a-chip.
By combining advanced simulation methods with a sophisticated proof engine, high-level primitives, and hierarchical state machines, the suite builds verification into the design process. As a result, designers are better equipped to weed out functional errors in their designs early in the cycle.
In addition, the suite makes it possible to construct a "golden" reference model for the functional design specification in text and/or graphics, which can then be used throughout the flow. Such a model permits improved communication between hardware and software teams and between customers and suppliers.
Version 5.2 adds scalable, modular, and hierarchical design flows to handle designs of unlimited size. It also offers enhanced datapath expressions and exact arithmetics, with static detection of unsigned overflows for safer, better, optimized designs.
Esterel Studio 5.2 is available in local-area and wide-area network configurations. One-year time-based licenses start at $33,000.