High-level synthesis (HLS) continues to grow in favor among beleaguered system-on-a-chip (SoC) design teams. At the same time, EDA vendors continue to increase the capabilities of their tools. The latest example, the Mentor Graphics Catapult C synthesis tool, has added support for SystemC synthesis to augment its existing support for pure untimed ANSI C++.
Catapult C has grown steadily in its capabilities since its introduction several years ago, most recently adding control-logic synthesis and low-power optimizations at last year’s Design Automation Conference. In the meantime, EDA vendors such as Mentor have seen the HLS market grow. Yet that market remains divided on the input language with which it feeds HLS tools. There’s the ANSI C/C++ camp on one side, and there’s the SystemC camp on the other.
According to Shawn McCloud, product line director for Catapult C, even the SystemC camp itself is fragmented. “Some designers don’t give much thought to the fact that SystemC spans multiple levels of abstraction,” says McCloud. A survey of SystemC users last summer shows that although SystemC was initially conceived as a vehicle for cycle-accurate modeling, 65% of SystemC users employ it for transaction-level modeling (TLM) work.
“So even though a majority of System C use is for modeling at system level, the abstraction level being used is TLM,” says McCloud. “When you look at this from a synthesis perspective, it’s cycle-accurate. But that’s not what TLM devotees want to use because it’s too slow.”
Mentor’s addition of SystemC support to Catapult C brings the ability to specify complex bus interfaces for connections between an SoC’s processor(s) and peripherals. In doing so, McCloud contends that the tool bridges the ESL and RTL flows in a way that it hasn’t until now. “More importantly, we have unified the HLS input languages by providing support for multi-language, multi-abstraction capability,” says McCloud.
As a result, Catapult C is better positioned to address full-chip design requirements. The tool supports cycle-accurate SystemC synthesis with fine-grained control over input when users need it. The SystemC support allows the tool to read in legacy synthesizable SystemC IP, of which there is quite a bit now amassed throughout the industry. It also handles transaction-level SystemC synthesis, with support for some of the more abstract communications constructs in SystemC. This aspect of the tool’s SystemC support is compatible with the TLM 2.0 standard.
Having support for both ANSI C++ and SystemC within a single HLS tool resolves the “language dilemma” that designers have faced. “Users see the advantages of untimed C++, which is highly abstract and lightweight. On the other hand, SystemC provides more control over input source code. Now they can take advantage of the respective strengths of both languages,” says McCloud. Catapult C can be plugged into existing SystemC methodologies, and designers can choose the style of coding that fits their company culture and methodology.
Catapult C supports all of the powerful constructs in SystemC that enable the modeling of hierarchy, concurrency, timing, data types, and communications. It also supports cycle-accurate SystemC code, a style that represents a natural evolutionary step for RTL coders. Any mixed-language simulator, such as Mentor Graphics’ Questa, can be used to view waveforms from the SystemC code in simulation as one would when simulating Verilog or VHDL.
When coupled with Mentor’s other ESL tools, Catapult C (see the figure) offers a continuous path from the system level to implementation through synthesis. Most notably, Vista Architect, a TLM 2.0-based platform for architecture design, analysis, and verification, provides the environment in which designers can model and debug complete systems. It can then generate TLM 2.0 models and deliver a platform with which those models can be subjected to architecture-level tradeoffs of power, performance, and area. Once models are developed and verified, Catapult C offers the path to RTL.