All too often within the SoC world, system design isn't exactly... system design. Software and hardware design often come together too late to overcome problems. But some tools help meld the two earlier in the cycle.
Tenison EDA's newly expanded VTOC product line bridges hardware and software design by providing fast, automated abstraction of RTL to C++/SystemC. By doing so, the tools aid the process of full-system co-development and co-verification (see the figure).
In creating C++/SystemC models from RTL, the VTOC tools enable what Tenison calls "emulation in software." The tools generate cycle-accurate models that are C++ at their core, with a thin veneer of SystemC for interface purposes. This enables them to run considerably faster than RTL emulation.
The VTOC line is now available in modular form. One new option is VTOC Export, which lets users create models that run standalone without requiring a run-time license. As a result, models for a given project can be distributed to customers or other design teams without a run-time license from Tenison. This option runs with VTOC Generate, the tool that creates the models.
Another new option is VTOC Validate. Used with yet another option, VTOC Runtime, VTOC Validate compares the function and response of C++/SystemC models to the original RTL models. This provides a sanity check as a design moves from a hardware-centric to a system-centric view.
All VTOC options are available now. An annual VTOC Generate license is $75,000.