Electronic Design

Functional Verification Tool Gains Link To SystemVerilog Assertions

With the addition of a standard assertion-language link, the 360 Module Verifier (360 MV), a functional verification environment, is equipped to fully leverage both SystemVerilog assertions and Open Verification Library assertions.

The new SVA capability creates a gateway to 360 MV by using and reusing assertions created in formal- and simulation-based verification. Assertions and RTL code can be debugged using 360-MV’s debugging environment or via links to Novas Software’s debugging tools. The 360 MV supports a broad set of SVA assertions including advanced constructs such as local variables. It also supports the full OVL 2.0 standard. These links reduce overall verification efforts to ensure high module and IP quality. The new gateway is included in OneSpin’s recent version 4.3 release of 360 MV at no extra charge.

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