Meet in the Middle
Although top-down analog/mixed-signal (AMS) design methodologies have been promoted by academia for many years, few people use them, especially in the U.S. Analog-flavored HDLs like Verilog-AMS and VHDL-AMS see duty for testbench writing, block-level Spice acceleration, and compact device models. Far more common is a bottom-up design style, with verification of all of the transistor-level blocks at the top level. There is no universal approach for AMS design as there is in the digital world. Cadence recommends a hybrid "meet-in-the middle" approach that combines top-down design for speed of design closure with bottom-up design for accuracy in design verification.Start Top-Down
It's best to begin with a specification of the entire system that's captured in a set of VHDL or Verilog testbenches. Partition the design into a set of blocks and create basic models of these blocks with just enough detail to do reasonably accurate I/O modeling. The idea here is to verify block-to-block interconnects so the top-level specification can be checked. In a meet-in-the-middle approach, you want to avoid a full-blown bottom-up approach that gets bogged down in flat transistor-level detail early, which can quickly balloon into a design that's simply too difficult to verify. Meanwhile, testbenches should also be created for the blocks. The block models only need to be good enough to get design closure with the top-level specification.
The basic block models are Verilog table models that can be created using proprietary Cadence Verilog extensions or by other means. Legacy or third-party transistor-level IP can be converted to Verilog table models using the block testbenches. Converting the fixed transistor blocks will yield models that have the accuracy of Spice coupled with the speed of HDL, which is what you want in the top-down portion of the hybrid approach. Later, after the block-to-block interconnects are verified, you can push down into the blocks themselves with more bottom-up detail. Transistor-level representations of these blocks can be used in the verification stage if they're warranted.
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