Electronic Design

Goodbye Wireload Models, Hello Timing Correlation

Since its inception in the late 1980s, RTL synthesis has seen a parade of innovations intended to match the pace of silicon integration. Now Synopsys, which launched RTL synthesis with Design Compiler, has upgraded its flagship tool to eliminate wireload models and provide much tighter correlation between synthesis results and post-layout results.

Design Compiler 2005 addresses the issues of correlation between synthesis and implementation through what Synopsys calls "topographical technology." Essentially, DC 2005 brings physical intelligence into the synthesis engine.

The tool bases its timing estimations on a virtual layout done inside the synthesis engine and throughout the synthesis flow. This process starts at RTL and continues through to a final netlist. Timing and area estimations are updated as synthesis progresses and as the context for the estimations becomes more accurate.

To perform its magic, DC 2005 only requires access to the physical cell library that will be used in implementation. Armed with that physical information, DC 2005 can plow through the tradeoffs between, say, cells that have less leakage voltage but are slower than faster cells that leak more.

What results from those tradeoffs can be extremely good correlation between DC 2005's predictions for post-layout timing and area and what actually results from physical implementation (see the figure). DC 2005 delivers high-quality results while relieving the RTL designer of the need to be a physical-design expert or to change their synthesis methodology to achieve them.

DC 2005's capabilities are available in Synopsys' DC Ultra package, which costs $85,750 for a one-year technology subscription license. Users of the DC Expert package can upgrade to DC Ultra for $34,300 for a one-year license.

Synopsys
www.synopsys.com

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