Electronic Design

Graph-Based Test-Synthesis Tool Creates Verification Plans

The complexity of today's system-on-a-chip designs creates serious verification challenges in various respects. It's increasingly difficult to write an effective and comprehensive verification plan. Developing a set of test vectors is itself an enormous undertaking, with as many as 10 lines of code needed for each line of RTL in the design under test.

One way to approach this problem is a graph-based technique that breaks the verification problem down into a hierarchy combined with a set of dependencies. In its Trek functional test-synthesis tool, startup Breker Verification Systems looks to help with the daunting task of developing functional vectors. The tool also tackles the problem of understanding, defining, and analyzing verification requirements.

Earlier attempts at graph-based approaches to functional verification haven't panned out, as the graphs proved too large and unwieldy. Breker's tack, which is to combine graph-based techniques with a dependency resolution engine, provides graphical feedback to visualize the verification plan and analyze it for completeness and coverage before beginning simulation runs (see the figure). According to the company, this ensures the inclusion of all functional cases in the construction of the verification plan. The plan may be input in either graphical format or as source code.

The verification plan is then used to automatically generate test vectors, which provide input stimulus to the design and check that the output results are correct. Trek is compatible with testbench tools for SystemVerilog, Verilog, Vera, Specman, and SystemC.

Pricing for the Trek functional test-synthesis tool starts at $32,000 for one-year time-based licenses. The tool is available now.

Breker Verification Systems Inc.
www.brekersystems.com

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