Electronic Design

Hardware-Assisted Verification Platforms Tackle Complexity

In its three next-generation hardware-assisted verification platforms, Mentor Graphics seeks to address the growing complexity of today’s SoC designs through a combination of the price-performance point of FPGA-based systems and the interactive debug capabilities of custom ASIC-based systems. The Veloce Solo, Trio, and Quattro products are based on a new “emulation-on-chip” architecture enabling megahertz-class verification run-time speeds without compromising debug productivity and modeling accuracy for designs up to 128 million ASIC gates.

This new verification family delivers the industry’s fastest “target-less” and in-circuit emulation (ICE) capability that facilitates concurrent hardware-software validation and embedded system verification for key vertical market applications such as multimedia/graphics, computing, networking and wireless designs.

The Veloce product family addresses specific verification applications and use modes. The Veloce Trio series addresses high-performance transaction-based acceleration as well as plug-and-play, event-accurate simulation acceleration, and extends the product’s utility into embedded system verification. The rack-mountable, multi-user Veloce Trio addresses the needs of logic and system designers for up to 16 million ASIC gates in a data center-like environment. For single users, Veloce Solo addresses the needs of designers developing systems up to a complexity of 16 million ASIC gates in an acceleration or in-circuit emulation mode. Lastly, the multi-user Veloce Quattro is architected to address the needs of design teams developing systems up to a complexity of 128 million ASIC gates in an acceleration and/or in-circuit emulation mode.

Powered by an industry-proven 90-nm silicon process and Mentor’s patented VirtualWires technology, the new emulation-on-chip architecture delivers a 3X to 5X boost in runtime performance compared to Mentor’s previous hardware-assisted systems. This architecture also provides fast compile times of up to 15 million RTL equivalent gates per hour. Unlike other hardware-assisted tools based on commercially available FPGA technology, the Veloce compiler dramatically shortens the model build time.

The Veloce platform also enables simulation-like debug visibility on every signal in the design without compromising capacity or run-time speed. The faster turnaround time allows designers to execute numerous and longer tests to finish RTL and system-level validation with a higher degree of first-pass confidence.

The new Veloce family also addresses transaction-based acceleration. It delivers megahertz-class acceleration compliant with Accellera’s third-generation Standard Co-Emulation Modeling Interface (SCE-MI 2.0).

It is architected based on the SystemVerilog Direct Programming Interface to deliver up to 1000X performance improvement over the fastest software simulator without compromising interoperability. The new transaction compiler de-couples the software simulator from the high-performance Veloce family to accomplish an optimal mix of bandwidth and communication latency.

Veloce is shipping in volume production worldwide and supports the Linux platforms. Flexible business models are available including short-term rentals, long-term leases, and purchases. Monthly rental pricing for Veloce Trio starts at $21,000 (USD) for 8 million gate capacity.

Mentor Graphics
http://www.mentor.com/med

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish