In a move that comes as a surprise to the EDA community, Open Verilog International (OVI) and VHDL International (VI) have announced plans to unite. The resulting, and as yet unnamed, industry organization will be responsible for driving the worldwide development and use of hardware-description-language (HDL) standards. Such standards play a key role in enabling systems design. They also allow semiconductor and design-software companies to enhance their language-based design-automation processes.
This move is yet another example of the multilanguage usage trend currently sweeping the design industry. With company mergers and acquisitions on the upswing, it's not uncommon to have more than one in-house design group that has been trained using different design languages. Rather than choose one language over another, tool vendors have been working in conjunction with the design community. Together, they're actively devising ways to support language-independent design flows, methodologies, and tools.
Toward Interoperable Languages The unification move by OVI and VI sets a precedent for the development of future interoperable language standards. Rather than focus on easing the design process with one of the HDLs—Verilog or VHDL—the new organization will strive to meet the challenges of system-level design using both languages. The combined strength of OVI and VI will provide the impetus, momentum, and technical capabilities to ensure this happens.Over the next few months as the two come together, technical work undertaken by both organizations will continue. To help ease the transition, OVI and VI have discussed forming a working group committed to language interoperability between VHDL and Verilog HDL. Over the past few years, the two organizations have successfully cosponsored several technical working groups. Work on common standards has included Standard Delay Format (SDF), the IEEE 1481 Delay and Power Calculation System (DPCS), and the Advanced Library Format (ALF).
Other results of the effort have included Design Constraints, consistent ASIC function and timing support via the VHDL Initiative Toward ASIC Libraries (VITAL) and the Verilog HDL ASIC Task Force, and synthesis styles for VHDL and Verilog.
Officers for the new organization will be elected during the upcoming 37th Design Automation Conference in Los Angeles, June 5-9. To learn more about joining, contact either Dennis Brophy at (503) 526-1694 or [email protected], or Gabe Moretti at (303) 652-0195 or [email protected].