Today, up to 80% of new ASIC and FPGA designs reuse RTL code from previous designs, and many design teams are embracing SystemVerilog, which was built with design reuse in mind. To support the ongoing adoption of SystemVerilog, Mentor Graphics has retooled its HDL Designer series of products to provide a platform for SystemVerilog design and verification.
The HDL Designer Series product accelerates RTL design reuse and optimizes design creation, synthesis, and verification processes for complex ASIC and FPGA designs. The suite covers everything from design creation through functional verification with support for VHDL, C/C++, PSL, Verilog, mixed languages, and now SystemVerilog. HDL Designer integrates with Mentor’s ASIC and FPGA flows and supports applications including: simulation, formal verification, hardware-assisted emulation, synthesis, and place-and-route environments.
One important aspect of HDL Designer as it relates to SystemVerilog is its ability to tame the complexity of an object-oriented design style, which is an attractive element of migrating to SystemVerilog. The product also has facilities for documentation for design reviews, communications between design groups, and establishing an archival system for future reuse. Within minutes, designers can create an interactive Web site to describe designs both textually and graphically for effective design development and communications.
HDL Designer supports a number of SystemVerilog features, among them support for mixed languages and dialects as well as assertions and coverage reports. The suite also provides the ability to instance IEEE Std. 1800-2005 library components with Verilog-1995-compatible port descriptions in Verilog-1995 block-diagram and/or interface-based design to create structural design.
The HDL Designer suite with SystemVerilog support is available now with pricing starting at $6900.