HDL Tool Supports Mixed VHDL, Verilog And EDIF Simulation

To support the growing complexities of system-on-chip designs, a new HDL tool called Active-HDL/DL offers designers a complete, high-performance, mixed-language design verification environment. The new product is claimed to be the EDA industry's first HDL simulator that supports mixed VHDL, Verilog and EDIF simulation from a single simulation kernel.
Active-HDL/DL is based on the company's Dual Language + EDIF direct compile simulation kernel that offers built-in Vital Acceleration and Verilog primitives. With Active-HDL/DL designers can freely mix, simulate and debug VHDL, Verilog and EDIF at all levels of a design's hierarchy using a single simulator. The product features source code debugging, breakpoint setting, and the ability to single step through simulations to provide access to detailed information between VHDL and Verilog components.
The company's mixed simulation kernel technology uses unified elaboration of mixed designs, which compiles design data into a common database, and proprietary event scheduling algorithms for mixed types of code to achieve the highest level of performance. Case sensitive name differences are resolved between languages automatically.
Active-HDL/DL includes a Project Manager, HDL Editor, Block Diagram Editor, Automatic Testbench generator, Waveform Viewer/Editor, and mixed VHDL, Verilog and EDIF simulation kernel. Pricing starts at $9,800. A free evaluation copy is available.