Hierarchical SoC Design Tool Handles Over 25 Mgates

Most of today's system-on-a-chip (SoC) devices are designed in flat fashion. This is fine for designs with only about 10 million gates. But over the next few years, the ballooning gate counts and complexity of SoC designs are expected to force designers to address timing closure in a hierarchical fashion. Integration Ensemble (IE), Cadence Design Systems' first offering in its SuperChip Initiative, is a synthesis/place-and-route tool that enables a complete hierarchical flow from RTL to GDSII using a single user interface, single database, and single timing engine.

According to Cadence, IE is the first and only fully integrated, flat, and hierarchical timing-driven SoC design tool (Fig. 1). It will handle logical and physical designs with over 25 million gates of random logic (100 million or more transistors) in process geometries of 0.12 µm and smaller. IE also ensures timing-closure predictability by using new planning, budgeting, and implementation algorithms. Beyond that, it solves block-level timing-convergence problems and offers a new weapon for chip-level design and integration.

Typically, the SoC design process scatters test logic, buffers, and spare logic at the top level. This requires the ability to handle individual gates without having to group them physically in a separate level of hierarchy at the top level. IE supports such a design flow from RTL to GDSII. The environment, which handles top-down and bottom-up approaches to design, permits the inclusion of hundreds of thousands of cells at the chip level.

IE offers a hierarchical-block design flow, which supports a top-down approach to SoC design (Fig. 2). Chip-level routing is performed before the detailed synthesis process. Top-level timing is closed prior to beginning the individual block-level design implementation. The long wires at the top level are addressed by inserting global buffers and/or repeaters at the top level, eliminating the need for interblock time budgeting and allowing for concurrent implementation of blocks. Cadence says this approach also gives designers virtually unlimited capacity.

A number of new features contribute to IE's horsepower. First and foremost is Cadence's next-generation common database technology. The database handles 20 million or more gates and eliminates the requirement for data transfer between different tools, such as an LEF/DEF translation. This improves turnaround time by a factor of 10. The single database is two to 10 times smaller than earlier databases.

Logical and physical views are stored and shared in the database, reducing the need for logical-to-physical iterations. The tool offers improved engineering change order (ECO) support for last-minute changes, too.

Another key feature, dynamic floorplanning, enables concurrent design of soft blocks (or place-and-route units) where blocks would be compiled or built with the knowledge of the context of their usage. It ensures that top-down constraints and module-up implementation converge.

RTL floorplanning is based on design size estimation. Any inaccuracy during this critical step will invalidate the chip's floorplan and set the design team back in terms of time. These inaccuracies can come from a poor estimating tool that doesn't account for physical information; pure top-down or bottom-up pin optimization; unspecified RTL captured as a size estimate given by the designer; and last-minute ECOs, which are always tough to predict.

IE's dynamic floorplanner prevents estimation inaccuracies by accounting for physical effects. An in-context physical estimator based on Cadence's PKS synthesis technology drastically reduces the estimation-based inaccuracies. The floorplanner also adapts floorplans after block resizings occur. Block pins are placed hierarchically. The tool accounts for top-level topology as well as block-level constraints.

Dynamic timing abstraction is important, too. Using shell/core partitioning, it separates interface (shell) and internal (core) logic into different modules. The shell logic exists between the physical partition boundary and the first input register. On the output side, the last register to the physical partition boundary is marked as shell logic. The part of the design between the input and output registers is marked as core logic. When no registers are in the block or the logic doesn't pass through a register in that block, it's marked as shell logic.

While performing chip-level timing analysis and budgeting, shell/core separation dramatically improves capacity by only reading in the netlist for the shell modules. This leaves the core modules as "black holes," or those modules in the netlist for which no implementation or model is provided. In typical designs where the average large physical block contains 20% shell logic and 80% core logic, this analysis capability can provide a fivefold increase in capacity as well as significantly faster run times.

Dynamic timing abstraction typically provides twice as fast chip-level timing analysis with higher capacity. By focusing on the chip-level paths, dynamic timing abstraction automatically avoids analyzing paths contained within blocks. To benefit from this, designers only need to specify which blocks in the design should be abstracted and then perform normal timing analysis.

Cadence Design Systems Inc., 2655 Seely Ave., Bldg. 5, San Jose, CA 95134; (408) 943-1234; www.cadence.com.