My colleague was unhappy that the design was barely getting to 50 kHz after automated logic synthesis from RTL to gates. The design was targeted to run at 20 MHz. We inspected his Verilog code and reached a case statement in which the condition was a complex equation with several nested computations.
I was perplexed, knowing this wouldn’t work in hardware. In previous designs I was involved in, design entry had happened at the gate level or below. I sketched the schematic representing the design in question. It turned out Robert had never done design entry below RTL. He only knew C as a language to describe software and he had learned Verilog, but he did not have the hardware background to understand how one would implement it. He essentially was a software guy and was unaware of the implications of his coding.
From Gates To RTL
That’s when I realized the severity of the transition we were in and the importance of education as part of it. Logic synthesis had just been introduced as something new to this project in 1993. At the time, and largely to this day, RTL could only be written efficiently for implementation using logic synthesis with a fair amount of background in how an actual implementation will look. The problem my colleague was facing was that designers need to be able to imagine how registers, gates, and the transitions between them work. Pure language knowledge of Verilog is not enough.
All the transitions in EDA, from layout to transistors to gates to RTL, were motivated by complexity and needs for productivity improvement. With more silicon real estate available every year, productivity continually needed to increase to fill it. Every next level up required about 10 times less data entry than the level below, speeding design entry, reducing the risks of bugs, and allowing faster verification.
EDA tools always have taken care of the automated transition from level to level, verification at the next level up, and verification between abstraction levels. According to the International Technology Roadmap for Semiconductors (ITRS), the last 10 years have delivered productivity improvements of a factor of at least eight through better verification as well as small and large block reuse.
It’s The Software, Stupid!
So, where do we go from here? Even though the electronic system level (ESL) design market has grown to a respectable $200 million per year, its growth has not yet matched expectations set by analysts for the last 10 years. More recently, high-level synthesis (HLS) has become a bigger topic again, driven by the verification crisis. But why does the industry seem to be struggling to just move up in abstraction, given that the last transitions roughly happened every decade?
Originally, the next step seemed obvious. Just automate beyond RTL to the next level and replicate the step we did from gates to RTL using a next-step, high-level synthesis. I remember discussing this with Pierre Paulin, who published papers on HLS as early as 1986, at Munich Airport after DATE 2000. When asked over a good German beer when we will ever figure out high-level synthesis, he replied, “I think we already did. It’s called platform-based design.” The main issue now is that hardware developers are no longer developing alone. They also have to interact with software developers!
All the previous transitions were complexity-driven within the hardware domain, catering to the same set of users—hardware designers. Now software has a much bigger role, and with it the user base has changed. The next transition is no longer about hardware itself, but about hardware and software together. The crux of the current dilemma is the mixed new user base, with different attitudes, design traditions, and price expectations.
While transaction-level modeling (TLM) is often touted as the next level to automatically implement from, its details are not fully clear yet. More than 50% of a chip is reused today from commercial IP blocks or previous designs. The bulk of the issue has become chip assembly. For the building blocks, especially in multimedia and wireless, HLS from C, C++, or SystemC has become a valid alternative. However, this is not the same C that software developers know.
Hardware knowledge, like in the last transition to RTL, is still fundamental. Also, the TLM level the HLS transition is working from is fundamentally different from the TLM level used to enable early software development. While the former is focused on implementable code, the latter optimizes simulation speed. The underlying models are not the same, and verification among them becomes a nightmare.
The Path How To Get There
To get to the next level, a new representation has to be found representing both hardware and software. For the time being, no single representation of hardware and software is really available, mostly because neither software nor hardware developers could use it because of lack of knowledge about the other’s respective domain.
Perhaps this is only the second step and we can get by for a while with keeping hardware and software implementation flows separate while providing strong connections between them. For example, virtual platforms enable early, pre-RTL software development combined with system prototypes using hardware accelerated verification to verify at more accurate levels of abstraction once RTL is available. Only time will tell.