Electronic Design

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With its spyglass predictive analysis tool, Atrenta Inc. gave register-transfer-level designers a means of checking their code against scores of design rules that predict downstream implementation and timing bugaboos. Now, the company has applied its predictive analysis technology to synthesis-related constraints in a new add-on option, Spyglass Constraints. The tool finds problems that often don't show up until after placement and routing.

A large system-on-a-chip (SoC) design can contain many thousands of constraints. Until now, the methods available for checking their correctness have been less than thorough. Like intellectual-property cores, constraints converge from multiple sources. As the block design teams on a large SoC design fan out to work on their individual pieces of the puzzle, they typically receive a set of constraints for their particular block. Spyglass Constraints can be used to check their developing constraints files before they even start to synthesize the block. Finding and fixing problems with constraint consistency can eliminate later synthesis iterations and the need to reverify the design.

The tool functions at multiple levels. At the block level, it can find many constraint issues that would translate into timing closure problems later on. Constraints can be checked to ensure that clock characteristics are consistent. Generated clocks can be verified as consistent with source clocks, for example.

As blocks are integrated together at the chip level, Spyglass Constraints can ensure that block-level constraints are consistent with top-level constraints. Block-level design teams may define multicycle paths or false paths on points that disappear in top-down, full-chip synthesis. The tool ferrets out these issues and helps designers rectify them.

Pricing for the Spyglass Constraints starts at $40,000. The product is in beta testing now, with production shipments beginning later this quarter.

Atrenta Inc.
(408) 453-3333 www.atrenta.com

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